Self-calibrating pipelined subranging analog-to-digital converte

Details Self-calibrating pipelined subranging analog-to-digital converte Self-calibrating pipelined subranging analog-to-digital converte

1988-11-25

1990-01-16

Shoop, Jr., William M.

Coded data generation or conversion

Converter calibration or testing

341155, H03M 110

Patent

active

048946567

ABSTRACT:
An approach to A/D converter architecture is based on a "pipelined and submerged" architecture which includes a pipeline of elemental stages (10.sub.i). Each stage of the pipeline comprises a low-resolution flash A/D subconverter (12), a D/A converter (14), and a unity-gain buffer (16). To minimize converter nonlinearity due to component mismatches, a self calibration technique based on an "interpolation" scheme is used. This technique employs an on-chip delta-sigma A/D converter (32) to provide the reference for calibration and a 100-bit memory (50) to store nonlinearity information. Long term drift is corrected by a calibrator (34) in parallel with data conversion.

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patent: 4371868 (1983-02-01), Van de Grift et al.
patent: 4700174 (1987-10-01), Sutherland et al.
Lee et al., "A Self-Calibrating 15 Bit CMOS A/D Converter", IEEE J. of Solid-State Circuits, vol. SC-19, No. 6, pp. 813-819, Dec. 1984.
Dingwall et al., "An 8-MHz CMOS Subranging 8-Bit A/D Converter", IEEE J. of Solid-State Circuits, Dec. 1985, pp. 1138-1143.
Lewis et al., "A Pipelined 5-Msample/s 9-Bit Analog-to-Digital Converter", IEEE J. of Solid-State Circuits, Dec. 1987, pp. 954-961.
Takemoto et al., "A Fully Parallel 10-Bit A/D Converter with Video Speed", IEEE J. of Solid-State Circuits, Dec. 1982, pp. 1133-1138.

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