Coded data generation or conversion – Converter calibration or testing
Reexamination Certificate
2005-12-23
2009-06-02
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Converter calibration or testing
C341S144000
Reexamination Certificate
active
07541953
ABSTRACT:
One apparatus includes an array of current sources, a digital memory, and a calibration circuit. The digital memory is configured to store one set of digital calibration values for each of the current sources and to apply each stored set of digital calibration values to the corresponding current source to set the output current of the corresponding output current source. The calibration circuit is configured to update each set of digital calibration values in the memory in a manner that reduces mismatches between output currents of different ones of the current sources.
REFERENCES:
patent: 2457220 (1948-12-01), Fowler et al.
patent: 2618420 (1952-11-01), Levine
patent: 2706072 (1955-04-01), Furno
patent: 3677437 (1972-07-01), Haigler
patent: 4835535 (1989-05-01), Shibayama et al.
patent: 5522512 (1996-06-01), Archer et al.
patent: 5761877 (1998-06-01), Quandt
patent: 5771657 (1998-06-01), Lasher et al.
patent: 5873488 (1999-02-01), Guerra
patent: 5897024 (1999-04-01), Coughlin et al.
patent: 5955980 (1999-09-01), Hanna
patent: 6130632 (2000-10-01), Opris
patent: 6166670 (2000-12-01), O'Shaughnessy
patent: 6260695 (2001-07-01), Tasber et al.
patent: 6318051 (2001-11-01), Preiss
patent: 6331830 (2001-12-01), Song et al.
patent: 6363687 (2002-04-01), Luciano et al.
patent: 6578734 (2003-06-01), Coughlin et al.
patent: 6581356 (2003-06-01), Kim
patent: 6633301 (2003-10-01), Dallas et al.
patent: 6738000 (2004-05-01), Boxho
patent: 6805259 (2004-10-01), Stevens et al.
patent: 6847568 (2005-01-01), Gogl et al.
patent: 6885958 (2005-04-01), Yaklin
patent: 6925774 (2005-08-01), Peterson
patent: 7019677 (2006-03-01), Soman et al.
Cong, Y. et al., “A 1.5-V 14-Bit 100-MS/s Self-Calibrated DAC,” IEEE Journal of Solid-State Circuits, vol. 38, No. 12, Dec. 2003, pp. 2051-2060.
Bugeja, A.R. et al., “A Self-Trimming 14-b 100-MS/s CMOS DAC,” IEEE Journal of Solid-State Circuits, vol. 35, No. 12, Dec. 2000, pp. 1841-1852.
Groeneveld, D.W.J. et al., “A Self-Calibration Technique for Monolithic High-Resolution D/A Converters,” IEEE Journal of Solid-State Circuits, vol. 24, No. 6, Dec. 1989, pp. 1517-1522.
Chen Hsin-Hung
Lee Jaesik
Alcatel-Lucent USA Inc.
Jean-Pierre Peguy
McCabe John F.
LandOfFree
Self-calibrating current source arrays does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Self-calibrating current source arrays, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self-calibrating current source arrays will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4078597