Self-calibrating circuit of high speed comparator

Details Self-calibrating circuit of high speed comparator Self-calibrating circuit of high speed comparator

2000-12-28

2001-11-20

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S068000

Reexamination Certificate

active

06320426

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application Ser. No. 89127056, filed Dec. 18, 2000.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a comparator. More particularly, this invention relates to a comparator having the self-calibration function of eliminating the input offset voltage.
2. Description of the Related Art
In various kinds of analog/digital converters (ADC) such as flash ADC, interpolation ADC, pipeline ADC and two-step ADC, a high speed comparator is often required to fulfill the requirements of high speed operation of the digital circuit.
FIG. 1
shows a circuit diagram of a conventional comparator. In
FIG. 1
, a PMOS latchp
1
114
, a PMOS latchp
2
112
, an NMOS latchn
1
120
and an NMOS latchn
2
118
are a set of regeneration stage circuits in the comparator
128
. A PMOS resetp
1
116
and a PMOS resetp
2
110
are a set of reset circuits. An NMOS minm
122
and an NMOS minp
124
are a set of analog signal amplifiers, and an NMOS strb
126
is a switch determining whether the current of the whole comparator
128
is conducted.
In
FIG. 1
, when the low level latch signal is input from the latch terminal of the comparator
128
, the NMOS strb
126
is open, and the NMOS resetp
1
116
and the PMOS resetp
2
110
are conducted. Thus, the output terminals outp and outm are reset to a voltage of vdda. When a high level latch signal is input from the latch terminal of the comparator
128
, the NMOS strb
126
is conducted, and the NMOS resetp
1
116
and the PMOS resetp
2
110
are open. Therefore, the PMOS latchp
1
114
, the PMOS latchp
2
112
, the NMOS latchn
1
120
and the NMOS latchn
2
118
are regenerating. The input analog signal at the input terminal inp of the NMOS minp
124
is compared to the input analog signal at the input terminal inm of the NMOS minm
122
until the potential levels between the output terminals outp and outm are distinguished from each other.
If mismatch occurs to the NMOS minm
122
and the NMOS minp
124
, or to the PMOS latchp
1
114
, the PMOS latchp
2
112
, the NMOS latchn
1
120
and the NMOS latchn
2
118
of the regeneration circuit, a large input offset voltage is caused at the input terminals inp and inm. The accuracy of the comparator
128
is thus seriously affected. In the actual circuit design, one can increase the transistor size to reduce the degree of mismatch, however the fabrication cost is raised, the power consumption is increased, and the operation speed is reduced (since the parasitic capacitance is increased).
SUMMARY OF THE INVENTION
The invention provides a self-calibrating circuit of a high speed comparator. The self-calibrating circuit provides a self-calibration when the comparator is just turned on to eliminate the input offset voltage of the comparator.
The self-calibrating circuit of the high speed comparator is supplied with a power by a first and a second voltage source. The self-calibrating circuit comprises a latch control terminal, a first analog input terminal, a second analog input terminal, a first digital output terminal and a second digital terminal. The latch control terminal receives a latch signal, the first analog input terminal receives a first analog signal, the second analog input terminal receives a second analog signal. The first digital output terminal outputs a first digital signal, the second digital output terminal outputs a second digital signal.
The self-calibrating circuit further comprises first to fourth negative phase logic switches, first to fifth positive phase logic switches, a first and a second current source circuits, and a control logic circuit. The first negative phase logic switch comprises a power source terminal coupled to the first voltage source, a load terminal coupled to the first digital output terminal, and a control terminal coupled to the latch control terminal. The second negative phase logic switch comprises a power source terminal coupled to the first voltage source, a load terminal coupled to the first digital output terminal, and a control terminal coupled to the second digital output terminal. The first positive phase logic switch comprises a power source terminal coupled to the first digital output terminal, a control terminal coupled to the second digital output terminal, and a load terminal. The second positive phase logic switch comprises a power source terminal coupled to the load terminal of the first positive phase logic switch, a control terminal coupled to the first analog input terminal, and a load terminal. The third negative phase logic switch comprises a power source terminal coupled to the first voltage source, a load terminal coupled to the second digital output terminal, and a control terminal coupled to the latch control terminal. The fourth negative logic switch comprises a power source coupled to the first voltage source, a load terminal coupled to the second digital output terminal, and a control terminal coupled to the first digital output terminal. The third positive phase logic switch comprises a power source terminal coupled to the second digital output terminal, a control terminal coupled to first digital output terminal, and a load terminal. The fourth positive output terminal comprises a power source terminal coupled to the load terminal of the third positive phase logic terminal, a load terminal coupled to the load terminal of the second positive phase logic switch, and a control terminal coupled to the second analog input terminal. The fifth positive phase logic switch comprises a power source terminal coupled to the load terminal of the second positive phase logic switch, a load terminal coupled to the second voltage source, and a control terminal coupled to the latch control terminal. The first current source circuit comprises a power source terminal coupled to the first voltage source, a load terminal coupled to the load terminal of the first positive phase logic switch, and a control terminal. The second current source circuit comprises a power source terminal coupled to the first voltage source, a load terminal coupled to the load terminal of the third positive phase logic switch, and a control terminal. The control logic circuit comprises a calibration control terminal to receive a calibration signal, a latch signal input terminal, a first data output terminal, a second output terminal and a digital signal input terminal. The latch signal input terminal is coupled to the latch control terminal. The first data output terminal is coupled to the data control terminal of the first current source circuit. The second data output terminal is coupled to the data control terminal of the second current source circuit. The digital signal input terminal is coupled to the first digital output terminal.
Using the above self-calibrating circuit in a high speed comparator comprising the first current source circuit, the second current source circuit and the control logic circuit, a self-calibration is performed within a very short time after the high speed comparator is turned on. Therefore, the input offset voltage of the high speed comparator can be eliminated.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 4602167 (1986-07-01), Yukawa
patent: 5032744 (1991-07-01), Wai Yeung Liu

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