Self-calibrating analog to digital converter

Details Self-calibrating analog to digital converter Self-calibrating analog to digital converter

1987-02-24

1991-06-25

Pellinen, A. D.

Coded data generation or conversion

Converter calibration or testing

341118, 341155, 330 9, H03M 110

Patent

active

050271164

ABSTRACT:
A self calibrating algorithmic analog-to-digital converter is disclosed for which the gain of the conversion loop is precisely adjusted and controlled by an array of switched capacitors such control being stored in a latch. The offset of the gain stage is reduced by reducing the amount of charge injected from the gate of the input zeroing MOS switch.

REFERENCES:
patent: 3842413 (1974-10-01), LaGarde
patent: 4364027 (1982-12-01), Murooka
patent: 4417160 (1983-11-01), Schade, Jr.
patent: 4429282 (1984-01-01), Saari
patent: 4517549 (1985-05-01), Tsukakoshi
patent: 4529965 (1985-07-01), Lee
patent: 4543534 (1985-09-01), Temes et al.
patent: 4555668 (1985-11-01), Gregorian et al.
David P. Laude and James D. Beasom, "5 V Temperature Regulated Voltage Reference", pp. 1071-1075, IEEE Journal of Solid State Cir., vol. SC-15, No. 6, Dec. 1980.

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