Self booting logical AND circuit

Details Self booting logical AND circuit Self booting logical AND circuit

1983-01-17

1986-02-11

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307269, 307443, 307482, 307578, H03K 19096

Patent

active

045700850

ABSTRACT:
A solid state logical "AND" circuit implementation in NMOS circuitry has clock pulse conditioning providing self booting voltage levels for ultra fast propagation times and minimal power dissipation, where memory row driver concepts are utilized and silicon area is minimized, and two, low impedance, non-overlapping clock pulses, normally present in the environment are utilized.

REFERENCES:
patent: 3518451 (1970-06-01), Booher
patent: 3573487 (1971-04-01), Polkinghorn
patent: 3651334 (1972-03-01), Thompson et al.
patent: 3935474 (1976-01-01), Komarek
patent: 4044270 (1977-08-01), Lesser
patent: 4316106 (1982-02-01), Young et al.

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