Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Utility Patent
1998-11-03
2001-01-02
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S066000, C327S077000
Utility Patent
active
06169424
ABSTRACT:
FIELD
Embodiments of the present invention relate to circuits, and more particularly, to sense amplifiers.
BACKGROUND
Fast and robust data communication among components of a computer system, or between and among execution units in one or more processors, is increasingly important as clock speeds increase and as processor core voltages decrease.
FIG. 1
is a high-level diagram where driver
102
transmits data to receiver (or differential comparator)
104
via transmission line
106
. Receiver
104
may comprise a sense amplifier, followed by an inverter or buffer to provide a logic output voltage. Transmission line
106
may be the physical layer of a bus. The terms bus and transmission line will often be used interchangeably. Bus
106
may be, for example, a GTL (Gunning Transceiver Logic) bus or a CTC (Center Terminated CMOS) bus. The output voltage at terminal
108
of receiver
104
will usually be a logic voltage representing one of the two Boolean elements “1” and “0”. Implicitly indicated in
FIG. 1
is a reference voltage source for providing a reference voltage V
ref
, where usually V
ref
<V
cc
. The voltage at input terminal
110
of receiver
104
is denoted as V
in
. The output voltage of receiver
104
is indicative of V
in
−V
ref
, where the output is one of the two Boolean elements when V
in
>V
ref
and is the other of the two Boolean elements when V
in
<V
ref
.
It is often desirable that the sense amplifier characteristics should not change appreciably for common mode voltage changes in V
in
and V
ref
. For example, it may be desirable for the output voltage delay of the sense amplifier to be insensitive to common mode voltage changes. This feature may be even more desirable when there are a plurality of sense amplifiers connected to a bus, because then it is easier to satisfy timing requirements. Also, sense amplifiers with reduced sensitivity to common mode voltage changes are less sensitive to variations in signal integrity induced by noise in the bus, and larger timing margins may be tolerated.
FIG. 2
is a schematic for prior art sense amplifier
200
, also called a pMOS (p-Metal Oxide Semiconductor) amplifier because the voltages V
ref
and V
in
are the gate voltages of pMOSFETs (p-Metal Oxide Semiconductor Field Effect Transistor)
202
and
204
, respectively. Transistors
206
and
208
comprise a matched current pair. Transistor
210
sources current. In
FIG. 2
, the gate of pMOSFET
210
is connected to the gates of transistors
206
and
208
so that pMOS amplifier
200
is self-biasing. The gate of pMOSFET
210
may be connected to an external bias circuit, not shown, but the connection as shown in
FIG. 2
is preferable because it eliminates the need for external biasing and provides feedback to compensate for process, temperature, and voltage variations. The output at node
216
may be connected to a CMOS (Complementary Metal Oxide Semiconductor) inverter (not shown) to provide a CMOS level output voltage.
Operation of pMOS amplifier
200
may heuristically be described as follows. Because the drain-source current of transistors
204
and
208
are essentially equal (ignoring loading at node
216
), the output voltage at node
216
, which is the drain voltage of nMOSFET
208
, will adjust so that nMOSFET
208
pulls the same current as pMOSFET
204
. However, pMOSFET
208
is biased by nMOSFET
214
to provide a nearly constant current sink when both are in saturation. That is, pMOSFET
208
provides a very high dynamic impedance, or active load, to pMOSFET
204
. If V
in
>V
ref
, then pMOSFET
204
will pull less current. For nMOSFET
208
to pull less current, its drain voltage (the output voltage at node
216
) will decrease so that nMOSFET
208
sinks less current. If V
in
<V
ref
, then the source-drain current of pMOSFET
204
increases and the drain voltage of nMOSFET
208
will increase so that nMOSFET
208
sinks more current.
FIG. 3
is a schematic for prior art sense amplifier
300
, also called a nMOS amplifier because the voltages V
in
and V
ref
are the gate voltages of nMOSFETs
302
and
304
, respectively. Transistors
306
and
308
comprise a current mirror. Transistor
310
sinks current, and its gate is connected to the gate of pMOSFET
306
so that nMOS amplifier
300
is self-biasing, again eliminating the need for external biasing and providing feedback to compensate for process, temperature, and voltage variations.
The operation of sense amplifier
300
is similar to sense amplifier
200
and may be heuristically described as follows. Transistors
306
and
308
are configured as, a current mirror pair so that pMOSFET
308
provides an active load to nMOSFET
302
. Ignoring loading on output node
312
, transistors
308
and
302
have the same source-drain current. If V
in
>V
ref
, the source-drain current of nMOSFET
302
increases and the drain voltage of pMOSFET
308
(which is the output voltage at node
312
) decreases so that pMOSFET
308
can provide more current. If V
in
<V
ref
, the source-drain current of nMOSFET
302
decreases and the drain voltage of pMOSFET
308
increases so that pMOSFET
308
sources more current.
FIG. 4
is a schematic for prior art sense amplifier
400
, also called a CMOS amplifier because the voltages V
in
and V
ref
are the gate voltages of CMOS inverters
402
and
404
, respectively. Transistors
406
and
408
respectively source and sink current, and their gates are connected to each other and to node
410
of CMOS inverter
404
so that CMOS amplifier
400
is self-biasing. When V
in
transitions above V
ref
, the gate-source voltage of nMOSFET
416
increases, and its source-drain current increases. Because transistors
402
and
416
have the same source-drain current (ignoring loading on the output node
412
), the drain voltage of pMOSFET
402
, which is the output voltage at node
412
, will decrease so that pMOSFET
402
can source more current. By similar reasons, the output voltage will increase when V
in
transitions below V
ref
.
For some bus topologies, the logic voltages may not be symmetrical about V
cc
/2. For example, for a Gunning Transceiver Logic bus, V
ref
=(⅔)V
cc
. Thus, the reference voltage V
ref
may vary due to different bus topologies. Furthermore, as data rates increase there may be more noise on the input voltages. Thus, as discussed earlier, it may be desirable for sense amplifiers to have a relatively wide common mode input voltage range.
As will be discussed later when presenting simulation results, the pMOS sense amplifier of
FIG. 2
may have an output delay for a rising output that is approximately 1000 ps (pico-seconds) for a common mode voltage range of 0.1 volts, whereas the output delay for a falling output at the same common mode voltage may be less than 200 ps. This variation in output delays for rising and falling outputs may cause timing problems. Furthermore, the pMOS sense amplifier may not even work for common mode voltages above 0.1 volts.
For the case of the nMOS sense amplifier of
FIG. 3
, simulations have shown that the output delay for a falling output may be approximately 450 ps and the output delay for a rising output may be less than 150 ps at a common mode voltage of −0.4 volts.
For the CMOS sense amplifier, its gain is highest at V
ref
≈V
cc
/2. Variations in V
ref
or input voltage swings may cause unwanted variations in timing, and the CMOS sense amplifier's common mode input range is relatively limited. Simulations have shown that the CMOS sense amplifier may have an output delay for a falling output of approximately 600 ps and an output delay for a rising output of less than 150 ps at a common mode voltage of 0.2 volts.
Consequently, there is a need for high-speed sense amplifiers that provide relatively smaller variations in output delays for wider common mode voltage ranges than in previous prior art sense amplifiers.
REFERENCES:
patent: 4536662 (1985-08-01), Fujji
patent: 4769564 (1987-11-01), Gardo
patent: 5162681 (1992-11-01), Lee
patent: 5864254 (1999-
Intel Corporation
Kalson Seth Z.
Tra Quan
Tran Toan
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