Self-biasing, low voltage, multiplying DAC

Details Self-biasing, low voltage, multiplying DAC Self-biasing, low voltage, multiplying DAC

1997-06-11

1998-11-10

Williams, Howard L.

Coded data generation or conversion

Analog to or from digital conversion

With particular solid state devices

341136, 341144, H03M 166

Patent

active

058350390

ABSTRACT:
A multiplying digital-to-analog converter produces first and second output currents that have a magnitude difference equal to a gain value multiplied by a magnitude difference between first and second input currents. The multiplying digital-to-analog converter has first and second input nodes for carrying the first and second input currents and first and second output nodes for carrying the first and second output currents. A first input transistor has a first terminal coupled to the first input node, a second terminal with voltage that increases with increases in the first input current, and a third terminal for carrying a first input bias current. A second input transistor has a first terminal coupled to the second input node, a second terminal with a voltage that increases with increases in the second input current, and a third terminal for carrying a second input bias current. A first output transistor has a first terminal coupled to the first output node, a second terminal coupled to a second terminal of the first input transistor, and a third terminal for carrying a first output bias current. A similar second output transistor has a third terminal for carrying a second output bias current. A first output bias circuit between a reference voltage and the third terminals of the first and second output transistors includes a gate transistor receiving a gate input signal, wherein the gate transistor is the only element in the first output bias circuit that is capable of receiving a signal other than the first and second output bias currents and the reference voltage.

REFERENCES:
patent: 4563670 (1986-01-01), Stallkamp et al.
patent: 5369406 (1994-11-01), Hughes
patent: 5739780 (1998-04-01), Cheng et al.

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