Self-biasing input stage for high-speed low-voltage communicatio

Details Self-biasing input stage for high-speed low-voltage communicatio Self-biasing input stage for high-speed low-voltage communicatio

1992-07-14

1994-01-11

Sikes, William L.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307355, 307362, 307279, H03K 5153, H03K 326

Patent

active

052784673

ABSTRACT:
A circuit that includes a self-biased differential amplifier a level restore circuit. The output of the differential amplifier is coupled to the source pins of a p type transistor and an n type transistor. The output of the differential amplifier is further coupled to a first inverter circuit that provides feedback to the gates of the p and n type transistors. The first inverter also further amplifies the output voltage of the differential amplifier. When the differential amplifier outputs a high voltage, the p transistor attempts to drain the output and pull the output voltage down. When the differential amplifier begins switching from a high voltage to a low voltage, the p transistor accelerates the voltage swing and decreases the propagation delay of the buffer circuit. Likewise, when the differential amplifier swings from a low voltage to a high voltage, the n type transistor reduces the propagation delay of the voltage swing.

REFERENCES:
patent: 3983412 (1976-09-01), Roberts et al.
patent: 4740714 (1988-04-01), Masaki et al.
patent: 4769564 (1988-09-01), Garde
patent: 4937476 (1990-06-01), Bazes
patent: 5223753 (1993-06-01), Lee et al.

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