Self biasing direct coupled data limiter

Details Self biasing direct coupled data limiter Self biasing direct coupled data limiter

1984-12-06

1986-12-23

Bookbinder, Marc E.

Pulse or digital communications

Repeaters

Testing

455343, 328169, 307351, 307540, 307358, 375 76, H04L 2714, H04L 2506, H04B 116

Patent

active

046317376

ABSTRACT:
An interface circuit is coupled between the last stage of an FSK receiver and a limiter to provide a biasing voltage signal to the limiter. The receiver includes a power saver circuit which supplies power on an interrupted basis. The interface circuit contains maximum and minimum detectors which derive and hold voltages corresponding to the maximum and minimum values of the discriminated signal from the receiver. These maximum and minimum corresponding voltages are averaged in a predetermined manner to provide the biasing voltage to the limiter. Thus, a proper bias voltage level can be accurately and quickly determined, and supplied to the limiter when power is supplied.

REFERENCES:
patent: 3838448 (1974-09-01), Garde et al.

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