Self-biased trinary input circuit for MOSFET integrated circuit

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307209, 307214, 307244, H03K 1908, H03K 1940, H03K 1718

Patent

active

039696332

ABSTRACT:
A trinary input circit for an MOSFET integrated circuit includes a biasing stage formed by using a standard inverter, whose output is connected to its input so as to establish a particular bias voltage level when the input to the trinary input circuit is left floating. The output of the biasing stage is applied to the inputs of a second inverter stage having a higher beta ratio than the bias stage and to the input of a third inverter stage having a lower beta ratio. The bias stage when left open circuited will seek a quiescent voltage which is above the switching threshold of the second stage and below the switching threshold of the third stage. Thus, as a result of the relative beta ratios of the three stages when the input to the bias stage is left open, the bias stage will seek a particular voltage level such that the high beta ratio stage produces a logic 0 output and the low beta ratio stage produces a logic 1 output. When a voltage greater than a certain value which is defined as a logic 1 is applied to the input, thus overriding the biasing stage, both the second and third inverter stages produce logic 0 outputs and, when a voltage less than a certain value which is defined as a logic 0 is applied to the input, to override the biasing stage, both inverters produce a logic 1. Three logic input conditions are therefore defined by two signals for use within the integrated circuit chip.

REFERENCES:
patent: 3609411 (1971-09-01), Ma et al.
patent: 3700981 (1972-10-01), Masuhara et al.
patent: 3832576 (1974-08-01), Proebsting
patent: 3836790 (1974-09-01), Becker
patent: 3851189 (1974-11-01), Moyer

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