Self-biased phased-locked loop

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C327S148000

Reexamination Certificate

active

11140684

ABSTRACT:
In general, in one aspect, the disclosure describes a phase-locked loop circuit. The circuit includes an oscillator having a first control input and a second control input, wherein the first control input and the second control input act to control output frequency of the oscillator. The circuit further includes a first charge pump and a second charge pump. A first bias generator is coupled to the first control input of the oscillator and can receive electrical input from the first charge pump and the second charge pump. A second bias generator is coupled to the second control input of the oscillator and can receive electrical input from the second charge pump and the first bias generator.

REFERENCES:
patent: 5727037 (1998-03-01), Maneatis
patent: 5877907 (1999-03-01), Tanishima et al.
patent: 6556088 (2003-04-01), Dietl et al.
patent: 6646512 (2003-11-01), Abassi et al.
patent: 6693496 (2004-02-01), Lebouleux
patent: 6710670 (2004-03-01), Maneatis
patent: 6753740 (2004-06-01), Gauthier et al.
patent: 6812758 (2004-11-01), Gauthier et al.
patent: 6859108 (2005-02-01), Abbasi et al.
patent: 6873214 (2005-03-01), Harwood
patent: 6894569 (2005-05-01), Fayneh et al.
patent: 6914490 (2005-07-01), Fayneh et al.
patent: 6922047 (2005-07-01), Knoll et al.
patent: 6937075 (2005-08-01), Lim et al.
patent: 6946917 (2005-09-01), Raha
Maneatis, John G., “FA 8.1: Low-Jitter and Process-Independent DLL and PLL Based on Self Biased Techniques”,1996 IEEE International Solid-State Conference, (1996), 3 pages.
Maneatis, John G., “Hidden Complexities of PLLs are Revealed”,Feature Article in Jan. 2002 Issue of ISD Magazine, (Jan. 2002), 5 pages.
Maneatis, John G., “Low-Jitter Process-Independent DLL and PII Based on Self-Biased Techniques”,IEEE Journal of Solid-State Circuits, vol. 31, No. 11, (Nov. 1996), 1723-1732.
Maneatis, John G., “Self-Biased High-Bandwidth Low-Jitter 1-to-4096 Multiplier Clock Generator PLL”,IEEE Journal of SOlid-State Circuits, vol. 38, No. 11, (Nov. 2003), 1795-1803.
Maneatis, John G., “Self-Biased High-Bandwidth Low-Jitter 1-to-4096 Multiplier Clock Generator PLL”, 688-690.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Self-biased phased-locked loop does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Self-biased phased-locked loop, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self-biased phased-locked loop will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3883594

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.