Self-biased phased-locked loop

Oscillators – Automatic frequency stabilization using a phase or frequency... – Tuning compensation

Reexamination Certificate

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Details

C331S017000, C331S025000, C331S185000, C327S157000

Reexamination Certificate

active

11321495

ABSTRACT:
In general, in one aspect, the disclosure describes a phase-locked loop circuit. The circuit includes an oscillator having a first control input, a second control input, and a third control input, wherein the first control input, the second control input, and the third control input act to control output frequency of the oscillator. The circuit further includes a first charge pump and a second charge pump. A first bias generator is coupled to the first control input of the oscillator and can receive electrical input from the first charge pump. A second bias generator is coupled to the second control input of the oscillator and can receive electrical input from the first charge pump, the second charge pump, and the first bias generator. A third bias generator is coupled to the third control input of the oscillator and can receive electrical input from the second charge pump and the first bias generator.

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Maneatis, John G., “Self-Biased High-Bandwidth Low-Jitter 1-to-4096 Multiplier Clock Generator PLL”,IEEE Journal of SOlid-State Circuits, vol. 38, No. 11, (Nov. 2003),1795-1803.
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Tan, Swee Boon, et al., “Self-Biased Phased-Locked Loop”, filed May 31, 2005; Serial No. 11/140,684, 21 pgs.

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