Self-biased phase locked loop

Details Self-biased phase locked loop Self-biased phase locked loop

2011-07-26

2011-07-26

Kinkead, Arnold (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

C331S183000, C331S185000, C331S034000

Reexamination Certificate

active

07986191

ABSTRACT:
A self-biased PLL includes a first charge pump and a second charge pump, an output terminal of the first charge pump is connected with a discharge-charge capacitor to output a control voltage, an output terminal of the second charge pump is connected with an output terminal of a bias generator for outputting a first bias voltage equal to the control voltage, wherein, a current output from the first charge pump is equal to a value obtained through dividing the production of a first constant with a bias current of a voltage control oscillator by a frequency division factor of a frequency divider; a current output from the second charge pump is equal to a value obtained through dividing the bias current of the voltage control oscillator by a second constant; and a multiple relation exists between an output resistance of the bias generator and an equivalent resistance of a differential buffer delay stage in the voltage control oscillator.

REFERENCES:
patent: 6873214 (2005-03-01), Harwood
patent: 7078977 (2006-07-01), Maneatis
patent: 7719328 (2010-05-01), Fu

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