Self-biased comparator with hysteresis control for power...

Details Self-biased comparator with hysteresis control for power... Self-biased comparator with hysteresis control for power...

2006-10-17

2006-10-17

Nguyen, Long (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S563000, C327S066000

Reexamination Certificate

active

07123057

ABSTRACT:
A voltage monitor circuit for biasing a well region of a CMOS circuit includes a self-biased comparator which compares first (INP) and second (INN) input signals. The comparator includes first (MN1) and second (MN2) N-channel transistors with grounded sources, a drain of the first N-channel transistor and a gate of the second N-channel transistor being coupled to a first output (OUTN), and a drain of the second N-channel transistor and a gate of the first N-channel transistor being coupled to a second output (OUTP). First (MP1) and second (MP2) P-channel transistors are operated to couple the second or first input signal to the second or first output, respectively, by controlling the gate-to-source voltage of the first or second P-channel transistor according to the polarity of a voltage difference between the first and second input signals.

REFERENCES:
patent: 5534800 (1996-07-01), Hiraki et al.
patent: 6066966 (2000-05-01), Kuo
patent: 6483353 (2002-11-01), Kim et al.
patent: 6501320 (2002-12-01), Le

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