Amplifiers – With semiconductor amplifying device – Including plural stages cascaded
Reexamination Certificate
2001-06-26
2003-02-04
Pascal, Robert (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including plural stages cascaded
C330S277000
Reexamination Certificate
active
06515547
ABSTRACT:
TECHNICAL FIELD
The present invention relates to power amplifiers, and more specifically, to an improved configuration for power amplifiers suitable for use in high-frequency applications.
BACKGROUND OF THE INVENTION
In state of the art MOS power amplifiers, the drain-gate voltage can often go as high as three times the supply voltage. This poses a limitation on the maximum supply voltage that can be used in such amplifiers and still avoid gate-drain breakdown. One method of ameliorating this problem is to utilize the familiar cascode structure in the amplifier, in which, in a two-transistor example, one transistor is in the common-source configuration and another is in the common gate configuration. In such cascode configuration the signal swing drops between the two transistors and therefore lessens the gate to drain breakdown problem. Such cascode transistors appear as a four terminal device: two gates, one source and one drain. Examples of such use of a cascode configuration are found in two pending applications recently filed (in 2000) by the present applicant, Tirdad Sowlati, entitled “CASCODE BOOTSTRAPPED ANALOG POWER AMPLIFIER CIRCUIT”, and “BOOTSTRAPPED DUAL-GATE CLASS E AMPLIFIER CIRCUIT”, respectively, the disclosures of each of which are incorporated herein by this reference as if fully set forth.
The cascode configuration thus requires two DC voltages, one for each of the gates. These DC voltages must be applied from sources external to the chip, therefore requiring an extra bond pad for the second gate, or alternatively, they must be generated on the chip requiring extra biasing circuitry.
A further condition in power amplifier applications is that it is very desirable to have the DC value which is applied to second gate to be equal to the supply voltage, thereby allowing a larger voltage swing on the drain. Thus, the second gate must have a DC connection to an off chip DC voltage source.
Thus, while the cascode configuration does ameliorate the gate-drain breakdown problem, it increases cost and complexity of the power amplifier. What would be a better solution is the ability to utilize the cascode configuration without the necessity of an additional DC voltage source for the gate of the second transistor. When more than one amplification stage is utilized, and/or differential amplifier structures are used, the resultant numerous cascode configurations multiply the DC voltage source problem.
In view of the above there exists a need in the art for an improved power amplifier configuration which has the stability provided by the cascode structure and yet does not require the extra DC connections needed to bias the two transistor gates for the standard cascode structure.
It is thus an object of the present invention to provide a power amplifier configuration that benefits from the unconditional stability provided by cascode structures, and yet at the same time does not require additional DC voltages supplied from off chip, or from extra biasing circuitry, to provide an additional DC biasing voltage on chip.
SUMMARY OF THE INVENTION
The above and other problems of the prior art are overcome in accordance with the present invention. A power amplifier is provided utilizing a self-biased cascode configuration, where the gate voltage of the common gate transistor of the cascode configuration is derived from its own drain. The self-biased cascode transistor appears as a compound transistor with three terminals and thus requires only DC voltage for the first gate (i.e. for the gate of the common source transistor). Due to the self biasing, the voltage of the second gate of the cascode pair is dynamically increased as its drain voltage is increased. The amount of increase can be chosen by appropriate selection of component values.
In such self-biased cascode amplifiers the combined transistors can withstand the larger voltage swing, thereby allowing the amplifier to be designed using a higher supply voltage with an increased output power. In preferred embodiments, the gate voltage of the second transistor of the self biased cascode structure is further boosted during the positive swing to more closely follow the rise in the drain voltage, to further achieve large signal swing with no gate-drain breakdown.
In an additional set of preferred embodiments the self-biased cascode amplifier configurations are expanded to differential structures and multi-stage differential power amplifiers. The amplifiers using the structure and method of the present invention can be designed in any of the standard classes of amplification, i.e. classes, A, B, C, and even switching class E.
These and other aspects of the invention will be apparent from, and elucidated with reference to, the embodiments described hereinafter.
REFERENCES:
patent: 5032799 (1991-07-01), Milberger et al.
patent: 5559472 (1996-09-01), Kobayashi
patent: 6137367 (2000-10-01), Ezzedine et al.
US 000260, U.S. Ser. No. 09/671,911, Filed: Sep. 28, 2000.
US 000265, U.S. Ser. No. 09/671,890, Filed: Sep. 28, 2000.
Biren Steven R.
Koninklijke Philips Electronics , N.V.
Nguyen Khanh Van
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