Self-biased bipolar ring-oscillator phase-locked loops with...

Oscillators – Automatic frequency stabilization using a phase or frequency... – Afc with logic elements

Reexamination Certificate

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Details

C331S008000, C331S017000, C331S025000

Reexamination Certificate

active

07746177

ABSTRACT:
Self-biased bipolar ring-oscillator phase-locked loops with a wide tuning range are disclosed. In a particular example, an apparatus to provide a phase-locked loop is described, comprising a voltage-controlled oscillator (VCO) to provide an output clock signal having a frequency, a quantizer, a phase-frequency detector to generate an adjustment signal, and a charge pump to modify the control voltage. The example VCO includes several ring-oscillator stages, where each ring-oscillator stage includes several gain stages to provide several output currents based on a comparison of a control voltage and several corresponding threshold voltages. The example quantizer includes several comparators to generate digital signals based on the output currents. The example charge pump modifies the control voltage based on the digital signals and the adjustment signal, and includes several switching elements to increase or decrease current to the charge pump based on the digital signals.

REFERENCES:
patent: 2006/0012442 (2006-01-01), Shinbo et al.
Maneatis et al., “Phase-Locked Loops Demystified,” Chip Estimate IP Connections Newsletter, True Circuits, Inc., Aug. 28, 2007, 4 pages.
Maneatis et al., “Self-Biased High-Bandwidth Low-Jitter 1-to-4096 Multiplier Clock Generator PLL,” IEEE Journal of Solid-State Circuits, Nov. 2003, 9 pages, p. 1795-1803, vol. 38, No. 11.
Maneatis, John G., “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques,” IEEE Journal of Solid-State Circuits, Nov. 1996, 10 pages, p. 1723-1732, vol. 31, No. 11.
Gilbert, Barrie, “The Multi-Tanh Principle: A Tutorial Overview,” IEEE Journal of Solid-State Cicuits, pp. 2-17, Jan. 1998, vol. 33, No. 1.

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