Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2002-08-09
2003-11-04
Callahan, Timothy P. (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S260000, C330S259000
Reexamination Certificate
active
06642791
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an amplifier circuit and a method for controlling the same. More particularly, the present invention relates to a self-biased amplifier circuit and a method for self-biasing an amplifier circuit.
BACKGROUND OF THE INVENTION
FIG. 1
schematically illustrates a conventional voltage follower circuit driving a combination of resistive and capacitive loads. As shown in
FIG. 1
, an input signal (V
in
) is applied to a non-inverting terminal, and an inverting terminal is coupled to an output terminal. There are a number of applications requiring a voltage follower circuit having low output impedance and capable of driving capacitive load. In many cases the load also includes a resistor in parallel with a large capacitor, for example, a resistive ladder in an analog-to-digital converter.
FIG. 2A
schematically illustrates an example of a conventional operational amplifier
10
which drives a resistive load R
L
and a capacitive load C
L
.
FIG. 2A
also depicts an example of how the amplifier
10
could be implemented using the CMOS process (NMOS and PMOS transistors). A typical technique to drive such loads is to use a single-stage operational amplifier which is compensated at its output (V
o
). As shown in
FIG. 2A
, the amplifier
10
includes input devices (M
1
and M
2
), and a current mirror circuit
12
which includes two PMOS devices M
3
and M
4
with the device ratio of 1:k. The current mirror circuit
12
provides a load current I
L
at the output terminal, which is ideally the same as a current i
1
(when k=1) flowing through the input device M
1
. In general, the load current I
L
is expressed as I
L
=k(i
1
+&Dgr;
1
), where &Dgr;
1
is an offset including a random offset of the devices due to process (and other uncontrollable factors) and a systematic offset.
However, the presence of an equivalent low resistor (R
L
) at the output terminal lowers the open-loop DC gain of the amplifier
10
. The low open-loop DC gain results in poor DC accuracy, which in turn leads to a systematic offset between the input V
in
and the output V
o
. For example, if the tail current (I
tail
), which is the sum of the currents flowing through the input devices M
1
and M
2
, is a constant bias current, then the varying load current (I
L
) with a varying input voltage V
in
(or a varying load resistance R
L
) results in a varying systematic offset between the input and output. A zero systematic offset only occurs when
I
tail
=
i
1
+
i
2
=
2
I
L
k
,
Where k is the device ratio of the PMOS transistors M
4
to M
3
as mentioned above. The DC power supply rejection is also poor because of the finite drain-source conductance g
ds
of the mirror transistors M
3
and M
4
.
One solution to increase the DC gain is to use a two-stage (or multi-stage) amplifier. The compensation of such multi-stage circuits typically involves the use of floating capacitors (e.g. pole-splitting or nested-miller techniques). However, floating capacitors may not be available in a standard CMOS process. Another solution may be the use of an adaptive biasing technique.
FIG. 2B
schematically illustrates a conventional amplifier circuit
14
employing such an adaptive biasing. As shown in
FIG. 2B
, the tail current of the differential pair M
1
and M
2
is adjusted according to the load current, and this technique also improves the open-loop DC gain performance. However, the amplifier circuit
14
still has a substantial offset because the gain is similar to that of a single-stage amplifier.
BRIEF DESCRIPTION OF THE INVENTION
An amplifier circuit includes a first input device coupled to a first input node and controlling a first current, a second input device coupled to a second input node and controlling a second current, a current source device coupled to a bias node and controlling a summed current of the first and second currents, a current mirror circuit, a first feedback circuit, a second feedback circuit, and a capacitor. The current mirror circuit generates a load current by mirroring the first current so as to provide an output signal voltage to an output node couple to the second output node. The first feedback circuit supplies a mirrored first current to the bias node, and the second feedback circuit pulls a mirrored second current from the bias node. The capacitor is coupled to the bias node and provides the bias voltage to the current source device.
REFERENCES:
patent: 4992756 (1991-02-01), Anderson
patent: 5650753 (1997-07-01), Ling
Callahan Timothy P.
LSI Logic Corporation
Luu An T.
Thelen Reid & Priest LLP
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