Self arc-extinguishing thyristor and method of manufacturing the

Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Combined with field effect transistor

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257137, 257139, 257144, H01L 2974, H01L 31111

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active

053450957

ABSTRACT:
A self arc-extinguishing thyristor having a large main current is disclosed. An n-type base layer is formed on a p-type anode layer. The n-type base layer includes in its top center portion a relatively heavily doped p+-type region which is surrounded by p-type region. A p-type base layer is locally coated at its top surface with a relatively thin first n-type emitter layer and a relatively thick second n-type emitter layer. A gate electrode buried in a gate oxide film is disposed on two channel regions and areas around the same. This structure suppresses a current amplification factor of a parasitic thyristor which is formed by the n-type base layer, the p-type region and the first n-type emitter layer, which in turn represses latching up of the parasitic thyristor.

REFERENCES:
patent: 4847671 (1989-06-01), Pattanayak et al.
patent: 4914496 (1990-04-01), Nakagawa et al.
3rd International Symposium On Power Semiconductor Devices and ICS, Apr. 1991, pp. 128-131, M. S. Shekar, et al., "Experimental Demonstration of the Emitter Switched Thyristor".
3rd Interantional Symposium On Power Semiconductor and ICS, Proceedings, Apr. 1991, pp. 132-137, H. Sumida, et al., "Numerical Analysis of Switching in the IGBT Triggered Thyristor".
Patent Abstracts of Japan, vol. 8, No. 198 (E-265)(1635), Sep. 11, 1984, & JP-A-59 086 262 May 18, 1984.

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