Self arbitrating auto resettable flag circuit

Details Self arbitrating auto resettable flag circuit Self arbitrating auto resettable flag circuit

1992-05-04

1994-05-24

Callahan, Timothy P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072722, H03K 526

Patent

active

053151844

ABSTRACT:
A flag setting, reading and clearing circuit is described which includes self arbitrating logic to provide priority for the flag setting portion of the circuit over the flag clearing portion. The flag is set by a set flag signal generated by a portion of a computer system to which the flag setting, reading and clearing circuit is a part. The set flag signal sets the flag by latching the voltage level of a voltage supply to a node in the circuit. A read status signal then latches the voltage at the node to another location which other portions of the computer system can access. At the same time, the read status signal clears the voltage level at the node unless the self arbitrating logic prevents it from doing so. The self arbitrating logic prevents the clearing portion of the circuit from clearing the flag when the set flag signal and the read status signal are both activated or HIGH at the same time. It does this by effectively canceling a control signal to the clearing portion of the circuit which is activated by the read status signal.

REFERENCES:
patent: 4620118 (1986-10-01), Barber
patent: 4968906 (1990-11-01), Pham et al.
patent: 4980577 (1990-12-01), Baxter
patent: 5038059 (1991-08-01), Ebzery et al.
patent: 5047658 (1991-09-01), Shrock et al.
"Digital Troubleshooting" by Richard Gasperini, pp. 9-2, 9-3, 1976, published by Movonics Company, Los Altos, Calif.

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