Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-09-04
2003-10-07
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S942000, C438S945000, C438S669000
Reexamination Certificate
active
06630408
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method for the creation of a cost-reduced phase shifting mask whereby further alignment problems that are typically experienced in creating a phase shifting mask are eliminated.
(2) Description of the Prior Art
The manufacturing of semiconductor devices requires the application of multiple diverse technical disciplines that collectively enable the continuing advancement of device performance that has been accomplished since the initiation of the semiconductor device. These various disciplines address various aspects of semiconductor device creation whereby. typically a plurality of active circuits is simultaneously created in a semiconductor substrate. To create a collection of circuits, commonly referred to as Integrated Circuit (IC) devices, the individual circuits are interconnected with metal leads. To further increase device density, multiple layers of interconnect metal can be created. These multiple layers of interconnect metal are separated by layers of dielectric or by insulating layers. Adjacent overlying layers of metal lines are interconnected by means of metal contact plugs or vias.
The semiconductor industry has, over the last several decades, been driven by a continued striving to improve device performance, which requires a continued decrease of semiconductor device feature size. In present day semiconductor devices, it is not uncommon to encounter feature size in the deep sub-micron range. With this decrease in device feature size, sub-micron metal interconnects become increasingly more important. A number of different approaches are used in the art for the formation of patterns of interconnect lines, most of these approaches start with the deposition of a patterned layer of dielectric, the pattern in the dielectric forms contact openings between overlying metal and underlying points of electrical contact. A layer of metal is deposited over the layer of dielectric and patterned in accordance with the required pattern of interconnect lines whereby the interconnect lines, where required, align with the underlying contact openings. The patterning of the layer of metal requires the deposition of a layer of photoresist over the layer of metal, the photoresist is exposed typically using photolithographic techniques and etched, typically using a dry etch process. The patterned layer of photoresist is removed after the interconnect metal line pattern has been created, leaving the interconnect line pattern in place. For sub-micron metal line sizes, these highlighted processing steps encounter a number of problems that are typical of device sub-miniaturization. These problems are problems of poor step coverage of the deposited metal (the metal should be evenly deposited and should fill the profile for the metal line with equal metal density), problems of etching (using dry etching, but metal such as copper and gold are difficult to plasma etch) and problems of step coverage and planarization for the overlying layer of dielectric.
Increased semiconductor device density frequently uses multi-level interconnections, the levels being separated by a layer of dielectric. Electrical contact between adjacent interconnect levels is established by creating vias or contact holes between these levels. It is clear that the contact holes must provide a dependable and low resistivity interconnect between adjacent levels of conducting lines. The reliability of the electrical connection that is established by means of a via or a contact hole must further not have any negative impact on device yield and performance.
Contact holes are typically formed in arrays of openings, the cross section of the contact holes can be a circle or a square or rectangular shape. Additional problems of creating uniform contact holes arise for application where the density of the array of contact holes varies over a relatively large surface area while these contact holes of various densities must be simultaneously created. These problems are further emphasized for sub-micron applications of 0.25 &mgr;m or less size contact holes. For these applications, the Attenuated Phase Shifting Mask (APSM) has found wide application whereby the APSM is applied using Deep Ultra Violet (DUV) light exposure. The phase shifting mask has shown promise and is increasingly used for applications where, due to small feature size or sharp variations in the density of the features that must be created, problems of Depth Of Field (DOF) are encountered. Increased semiconductor manufacturing requirements have also been met by increasing the size of the semiconductor substrate on the surface of which the semiconductor devices are created. This increase in size of the substrate brings with it problems of control of the Critical Dimensions (CD's) of created features over a relatively large surface area. The control of the CD at the edge of this large area has an impact on the control of the CD at the center of the large area. These impacts that are caused by variations in contact hole densities and by the use of relatively large surface areas into which contact holes must be created as yet pose a challenge for applications where APSM and DUV lithography are used.
The phase shifting mask makes possible the separation of images that are projected close to each other (cancellation of the proximity effect). For masks where no phase shifting is applied, the electrical field that is present at each of the apertures of the mask has the same phase at every aperture. Because of this and further emphasized by the diffraction and the limited resolution of the optical system that is used for the mask application, the diffracted waves of adjacent apertures will mutually enhance the field strength, causing a loss of CD of the adjacent features that are created by this conventional (no phase shifting) mask approach. By alternatingly applying a phase shifter (as part of the mask) between adjacent openings of the mask, the sign of the field of adjacent openings is reversed by the phase shifter. This eliminates the enhancement of the electric field of adjacent openings of the conventional mask, resulting in increased definition or control of the CD of the images that are created by the phase shifting mask.
Attenuating phase shifting masks are frequently used for the manufacturing of integrated circuit features, this especially for processing steps that have requirements of extremely closed alignment tolerances, that is in the submicron dimensional range.
Typical methods for the fabrication of phase shifting masks start with the surface of a semiconductor substrate over which a layer of chrome has been deposited. The layer of chrome is patterned with a layer of photoresist whereby the openings that have been created in the patterned layer of photoresist align with the openings that must be created in the deposited layer of chrome. The chrome is etched (removed from the surface of the substrate), after this the silicon surface of the substrate is etched creating the pattern of the phase shifting mask in the surface of the substrate. The photoresist and the chrome are removed, the mask that has been created in the surface of the substrate can be separated from the substrate by sawing.
Variations of this process can be made by using gray-tone masks that can be used to created gradated, three dimensional shapes in the surface of a substrate. A gray tone mask has regions that pass incident light in various degrees, allowing for etching the surface of the substrate to various depth and creating the three dimensional shapes. These three dimensional shapes can among others be used for the creation of vias.
A number of applications and patents have recently been made available that address attenuating phase shifting masks.
U.S. Pat. No. 5,897,979 (Tzu et al.) shows a process for an attenuating phase shifting mask.
U.S. Pat. No. 5,935,736 (Tzu) shows a process for an attenuating phase shifting mask that rem
Lin Ching-Chia
Tzu San-De
Ackerman Stephen B.
Everhart Caridad
Saile George O.
Taiwan Semiconductor Manufacturing Company
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