Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having substrate registration feature
Reexamination Certificate
2010-06-30
2011-11-15
Nguyen, Ha Tran T (Department: 2829)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having substrate registration feature
C438S412000, C438S424000, C438S427000, C438S421000, C257S506000, C257S510000, C257S522000
Reexamination Certificate
active
08058136
ABSTRACT:
A self-alignment method for a recess channel dynamic random access memory includes providing a substrate with a target layer, a barrier layer and a lining layer, wherein the target layer has shallow trench isolation structures; patternizing the lining layer, barrier layer and target layer to form recess trench channels; depositing a dielectric layer onto the recess trench channel; forming an ion doped region in the target layer; removing a portion of the dielectric layer to expose a portion of the recess trench channel; forming a filler layer covered onto the recess trench channel; removing a portion of the filler layer to expose a portion of the recess trench channel; forming a passivation layer onto the recess trench channel; removing the passivation layer on the lining layer; and removing the lining layer to form a plurality of structural monomers disposed at the recess trench channel and protruded from the target layer.
REFERENCES:
patent: 2005/0221580 (2005-10-01), Saitou et al.
patent: 2005/0239257 (2005-10-01), Sato et al.
patent: 2006/0273388 (2006-12-01), Yamazaki
patent: 2007/0114631 (2007-05-01), Sato et al.
patent: 2007/0170522 (2007-07-01), Lee et al.
Chen Chien-Hsun
Huang Chung-Lin
Lee Tzung Han
Inotera Memories, Inc.
Nguyen Ha Tran T
Rosenberg , Klein & Lee
Tran Thanh Y
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