Self aligning small scale integrated circuit semiconductor chips

Details Self aligning small scale integrated circuit semiconductor chips Self aligning small scale integrated circuit semiconductor chips

1984-04-12

1985-09-17

Hearn, Brian E.

Metal treatment

Stock

Ferrous

29580, 29583, 29589, 148 33, 148DIG28, 250553, 156657, 340719, H01L 2504, H01L 21302, H01L 2198

Patent

active

045423970

ABSTRACT:
Small scale integrated chips are fabricated from a semiconductor wafer and subsequently pretested and formed into large area arrays with self aligning and self locking characteristics due to the axial orientation of the semiconductor wafer and geometries employed for the chips based upon the wafer orientation, whereby the spacing of abutting chip edges in an array may be less than 7 .mu.m. The chips are fabricated from <110> axial wafer, e.g., silicon <110> axial wafer, wherein the chip boundaries are aligned with vertical {111} planes of the crystalline material so that each of the chips formed from the wafer may be defined within parallelogrammatic like geometries defined by these planes and their intersections. The term "parallelogrammatic like geometries" means all geometric shapes capable of being formed with various vertical {111} planes within the crystalline structure of the wafer. Examples of such shapes are parallelograms of various aspect ratios and variations or combinations of planar figures composed of parallelograms. Specific examples of geometries are diamond shaped or chevron shaped configurations.

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patent: 3869787 (1975-03-01), Umbaugh
patent: 3870850 (1975-03-01), Larionov et al.
patent: 3977071 (1976-08-01), Jarman
patent: 4170021 (1979-10-01), DuBois et al.
patent: 4253280 (1981-03-01), DuBois et al.
patent: 4278897 (1981-07-01), Ohno et al.
"Anisotropic Etching of Silicon", Kenneth E. Bean, IEEE Transactions on Electron Devices, vol. ED-25(10), Oct. 1978, pp. 1185-1193.
James B. Angell et al., "Silicon Micromechanical Devices", Scientific American, pp. 44-55, Apr. 1983.

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