Self-aligning ion-implantation method for semiconductor device h

Details Self-aligning ion-implantation method for semiconductor device h Self-aligning ion-implantation method for semiconductor device h

1989-09-18

1992-09-22

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 45, 437 49, 437 57, 437984, H01L 21265, H01L 2128

Patent

active

051496640

ABSTRACT:
A self-aligning ion-implantation method for forming multi-gate MOS transistor structures within a semiconductor cell array on a substrate is provided. Each structure includes a plurality of first gate electrode layers and a plurality of second gate electrode layers arranged in an alternating sequence over a channel region between a drain and a source region and insulated from each other. The method includes a step for forming the first gate electrode layers at uniform spaced intervals in that channel region; a step for ion implanting an impurity into a first predetermined channel region located below the space between two of said first gate electrode layers; a step for forming a second gate electrode layer in each space between two first gate electrode layers such that each second gate electrode layer overlaps a portion of the top surface of the two first gate electrode layers adjacent to it; and a step for forming a mask over two of said second gate electrode layers and ion implanting an impurity into a second predetermined channel region below a first gate electrode layer between the two second gate electrode layers, using the mask. The ion implantation is self-aligned due to the positioning of adjacent gate electrode layers.

REFERENCES:
patent: 4364167 (1982-12-01), Doncey
patent: 4397077 (1983-08-01), Derbenwick et al.
patent: 4818716 (1989-04-01), Okuyama et al.
patent: 4898840 (1990-02-01), Okuyama
patent: 4904615 (1990-02-01), Okuyama et al.

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