Self-aligning contact and interconnect structure

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

257382, 257774, 257900, 257904, H01L 2348

Patent

active

056568614

ABSTRACT:
An MOS transistor for use in an integrated circuit is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from a short circuiting to the gate by oxide insulation between the source/drain contacts and the gate, and a layer of silicon nitride above the gate. Contacts to the gate are made on top of the gate over the active region of the transistor because the source and drain regions are protected by a hardened layer of photoresist during etching of insulation to expose the gate contact. Source, drain and gate contacts are protected by a layer of titanium silicide so that interconnects are not required to completely cover these areas. Low resistance interconnects are formed of doped polysilicon covered by titanium silicide encapsulated by a thin film of titanium nitride.

REFERENCES:
patent: 4103415 (1978-08-01), Hayes
patent: 4325169 (1982-04-01), Ponder et al.
patent: 4409319 (1983-10-01), Colacino et al.
patent: 4466172 (1984-08-01), Batra
patent: 4466176 (1984-08-01), Temple
patent: 4470852 (1984-09-01), Ellsworth
patent: 4518629 (1985-05-01), Jeuch
patent: 4605470 (1986-08-01), Gwozdz et al.
patent: 4631806 (1986-12-01), Poppert et al.
patent: 4635347 (1987-01-01), Lien et al.
patent: 4654113 (1987-03-01), Tuchiya et al.
patent: 4657629 (1987-04-01), Bigelow
patent: 4746219 (1988-05-01), Holloway et al.
patent: 4772571 (1988-09-01), Scovell et al.
patent: 4774203 (1988-09-01), Ikeda eta l.
patent: 4774204 (1988-09-01), Havemann
patent: 4775550 (1988-10-01), Chu et al.
patent: 4783238 (1988-11-01), Roesner
patent: 4822749 (1989-04-01), Flanner et al.
patent: 4826781 (1989-05-01), Asahina et al.
patent: 4849369 (1989-07-01), Jeuch et al.
patent: 4851361 (1989-07-01), Schumann et al.
patent: 4855798 (1989-08-01), Inamura et al.
patent: 4868138 (1989-09-01), Chan et al.
patent: 4873204 (1989-10-01), Wong et al.
patent: 4877755 (1989-10-01), Rodder
patent: 4882297 (1989-11-01), Blossfeld
patent: 4886765 (1989-12-01), Chen et al.
patent: 4920037 (1990-04-01), Wei et al.
patent: 4937657 (1990-06-01), DeBlasi et al.
patent: 4939105 (1990-07-01), Langley
patent: 4944682 (1990-07-01), Cronin et al.
patent: 4946550 (1990-08-01), Van Laarhoven
patent: 4960729 (1990-10-01), Orbach et al.
patent: 4966864 (1990-10-01), Pfiester
patent: 4977100 (1990-12-01), Shimura
patent: 4978637 (1990-12-01), Liou et al.
patent: 4980020 (1990-12-01), Douglas
patent: 4985744 (1991-01-01), Spratt et al.
patent: 4996167 (1991-02-01), Chen
patent: 5013686 (1991-05-01), Choi et al.
patent: 5023204 (1991-06-01), Adachi et al.
patent: 5070037 (1991-12-01), Leisure et al.
patent: 5089865 (1992-02-01), Mitsui et al.
patent: 5359226 (1994-10-01), DeJong
Fu et al., "On the Failure Mechanism of Titanium Nitride/Titanium Silicide Barrier Contacts Under High Current Stress," 8093 IEEE Transactions on Electron Devices, vol. 35, No. 12, pp. 2151-2159.
Minami et al., "A New Soft-Error-Immune Static Memory Cell Having a Vertical Driver MOSFET with a Buried Source for the Ground Potential," IEEE Transactions on Electron Devices, vol. 36, No. 9, pp. 1657-1662.
"Self-Aligned Technique Employing Planarized Resist for Reducing Polysilicon Sheet Resistance by Formation of a Metal Silicide," 700 IBM Technical Disclosure Bulletin 30 (1987) Oct., No. 5, pp. 55-56. (Armonk, NY, USA).
Kusters et al., "Self-Aligned Bitline Contact for a 4 MBIT Dram," 1046B Extended Abstracts 87-1 (1987), pp. 289-290, Spring No. 1, (Philadelphia, PA, USA).
Yamanaka et al., "A 25 .mu.m.sup.2, New Poly-Si PMOS Load (PPL) SRAM Cell Having Excellent Soft Error Immunity," IEDM 1988, pp. 48-51.
Wolf et al., Silicon Processing for the VLSI Era, vol. 1: Process Technology, Lattice Press 1986, pp. 384-388, 423-454.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Self-aligning contact and interconnect structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Self-aligning contact and interconnect structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self-aligning contact and interconnect structure will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-162280

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.