Self aligned zero overlap charge coupled device

Details Self aligned zero overlap charge coupled device Self aligned zero overlap charge coupled device

1986-05-23

1987-07-07

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

29576W, 29578, 29580, 29591, 156644, 156653, 357 24, H01L 2100, H01L 2158, H01L 2160

Patent

active

046777377

ABSTRACT:
A self aligned, nonoverlapping gate structure for a charge coupled device is fabricated by depositing three sets of interleaved polysilicon gate electrodes. The first set of electrodes is applied in a planar form and sized to a width of about one-third the spacing of the electrodes of the first set. The second and third sets of electrodes are applied to overlap, in turn, portions of the previously applied electrodes. A thick shield layer of SiO.sub.2 is deposited and patterned atop the first and second sets of gate electrodes. After deposition of the third set of electrodes, the shield layers are removed to provide passageways extending beneath the overlapping portions of the second and third sets of electrodes. Such overlapping portions are then removed by etching through the passageways, to produce a nonoverlapping, generally planar gate structure.

REFERENCES:
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patent: 4503450 (1985-03-01), Brewer
patent: 4574468 (1986-03-01), Slotboom et al.
patent: 4614564 (1986-09-01), Sheldon et al.
IEEE Trans. on Electron Devices, vol. ED-21, No. 11, Nov. 1974, pp. 712-720, "Charge-Coupled Area Image Sense Using Three Levels of Polysilicon".

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