Self-aligned wafer or chip structure, and self-aligned...

Details Self-aligned wafer or chip structure, and self-aligned... Self-aligned wafer or chip structure, and self-aligned...

2011-06-28

2011-06-28

Andújar, Leonardo (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Chip mounted on chip

C257S738000, C257S780000

Reexamination Certificate

active

07969016

ABSTRACT:
A self-aligned wafer or chip structure including a substrate, at least one first concave base, at least one second concave base, at least one connecting structure and at least one bump is provided. The substrate has a first surface and a second surface, and at least one pad is formed on the first surface. The first concave base is disposed on the first surface and electrically connected to the pad. The second concave base is disposed on the second surface. The connecting structure passes through the substrate and disposed between the first and second concave bases so as to be electrically connected to the first and second concave bases. The bump is filled in the second concave base and protrudes out of the second surface.

REFERENCES:
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“Office Action of Japan Counterpart Application” issued on Aug. 24, 2010, p. 1-p. 3, in which the listed references were cited.

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