Self-aligned vias in an integrated circuit structure

Details Self-aligned vias in an integrated circuit structure Self-aligned vias in an integrated circuit structure

2002-08-05

2004-09-07

Wojciechowicz, Edward (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

C257S509000, C257S511000, C257S513000, C438S694000, C438S702000, C438S737000

Reexamination Certificate

active

06787875

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates in general to integrated circuits and, more particularly, to self-aligned vias in an integrated circuit structure.
BACKGROUND OF THE INVENTION
Interconnects are often formed in integrated circuit fabrication to connect particular elements or components of the integrated circuit and may be used, for example, to create an electrical path within an integrated circuit, such as to apply a voltage to a particular region or component of the integrated circuit. Interconnects may include one or more metal lines or wires and one or more vias. Metal lines may be formed in various structural layers called metalization layers and conductive vias may be formed to connect particular elements formed in various metalization layers. For example, conductive vias are often used to connect metal lines formed in one metalization layer with metal lines formed in other metalization layers.
Metal lines and vias may be formed using standard or damascene processes, such as single and dual damascene processes. In a standard process, metal lines are formed by depositing and etching away portions of a metal layer. In contrast, in a damascene process, metal lines are deposited in trenches formed in a dielectric layer and then excess material is removed, for example, by chemical metal polish (CMP).
SUMMARY OF THE INVENTION
In accordance with the present invention, a self-aligned via in an integrated circuit is provided that substantially eliminates or reduces the disadvantages and problems associated with previously-developed vias.
According to one embodiment, a method of forming a via in an integrated circuit is provided. The method includes forming a stack including a first layer, a hard mask layer, and at least one intermediate layer disposed between the first layer and the hard mask layer. The first layer comprises a first metal line. The method further includes forming a channel in the hard mask layer. The channel has a first side and a second side opposite the first side. The method further includes forming a resist layer having an opening extending over both the first and second sides of the channel. The method further includes forming a metal line trench and a via opening aligned with the first and second sides of the channel. The method further includes filling the metal line trench and the via opening with a conductive material to create a second metal line and a via connecting the second metal line with the first metal line.
According to another embodiment, a semiconductor apparatus is provided. The semiconductor apparatus includes a first layer, a second layer, and at least one intermediate layer disposed between the first layer and the hard mask layer. A first metal line is disposed in the first layer. A second metal line is disposed in a trench formed in the second layer. The trench has a first side and a second side opposite the first side. The semiconductor apparatus further includes a via connecting the first metal line with the second metal line. The via is formed such that it is self-aligned with the first and second sides of the trench.
Various embodiments of the present invention may benefit from numerous technical advantages. It should be noted that one or more embodiments may benefit from some, none, or all of the advantages discussed below.
One technical advantage of the invention is that a via connecting a first metal line with a second metal line may be self-aligned with the second metal line. Thus, the contact area between the via and the second metal line is equal to the entire cross-sectional area of the via, which may allow a desirable electrical contact between the via and the second metal line. In addition, the via has a relatively large contact area with the first metal line as compared with other methods of forming vias and metal lines. The via may have a larger contact area with the first metal line than a via formed using other fabrication methods, including other trench-first and via-first methods.
Another technical advantage is that vias and metal lines may be formed having desirable or increased spacing between adjacent vias and metal lines. This spacing may be greater than the spacing provided by prior trench-first fabrication methods, and may reduce or eliminate undesirable effects such as shorting or leakage current, for example.


REFERENCES:
patent: 2003/0003603 (2003-01-01), Chaudhry et al.

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