Self-aligned via using low permittivity dielectric

Details Self-aligned via using low permittivity dielectric Self-aligned via using low permittivity dielectric

1994-04-28

1996-10-15

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437231, 437235, 148DIG51, 1566531, 430317, H01L 21311

Patent

active

055653847

ABSTRACT:
A semiconductor device and process for making the same which reduces capacitance between adjacent conductors on a connection layer, reduces overetching due to via misalignment or uneven device topography, and maintains a rigid structure with good heat transfer characterisitics. In one embodiment, horizontal gaps between the patterned conductors 18 and 44 are substantially filled with an organic-containing dielectric material (Allied Signal 500 Series, for example) 22 and 54. Inorganic dielectric layers 24 and 56 are formed over organic-containing dielectric layers 22 and 54, respectively, from a material such as silicon dioxide. Vias are etched through the inorganic dielectric layers using an etch process such as fluorocarbons in a high density plasma which does not appreciably etch the organic-containing dielectric material.

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Translations of JP 3-105923, 4-311059 and 4-127454.
S. Wolf, "Silicon Processing For the VLSI Era" vol. II, pp. 214-217.

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