Self-aligned via and contact interconnect manufacturing method

Details Self-aligned via and contact interconnect manufacturing method Self-aligned via and contact interconnect manufacturing method

1994-11-08

1996-04-30

Quach, T. N.

Fishing, trapping, and vermin destroying

437228, 148DIG106, H01L 21283, H01L 21308

Patent

active

055125140

ABSTRACT:
An integral via structure and contact manufacturing process (10) with a first conductive layer patterning process section (12) that includes depositing a first conductive layer (34), creating a first via etch mask (44) on the first conductive layer (34), partially etching the exposed portions of the first conductive layer (34) to create first via structures (52) and a remaining first conductive layer (34), stripping the first via etch mask (44), masking the remaining first conductive layer (34) with a first layer etch mask (56) that covers the via structures (52), etching the exposed portions of the remaining first conductive layer (34) to form a first conductive pattern (60) having integral via structures (52). A first dielectric (72) is deposited and planarized to expose top portions of the first via structure (52) and a second conductive layer (90) is deposited, making contact with the first via structures (52). The second conductive layer (90) is patterned in the same manner as the first conductive layer (34) to create a second conductive pattern (102) with integral second via structures (98). A second dielectric layer (104) is deposited and planarized in the same manner as the first dielectric (72) exposing the second via structures (98). A third conductive layer is deposited, making contact with the second via structures (98) and patterned with convention methods to create a third conductive pattern (110). The process concludes with conventional passivation methods. The above mentioned steps may be repeated multiple times to form multiple, interconnected conductive layers.

REFERENCES:
patent: 4410622 (1983-10-01), Dalal et al.
patent: 4536951 (1985-08-01), Rhodes et al.
patent: 4614021 (1986-09-01), Hulseweh
patent: 4810332 (1989-03-01), Pan
patent: 4879257 (1989-11-01), Patrick
patent: 4914056 (1990-04-01), Okumura
patent: 4917759 (1990-04-01), Fisher et al.
patent: 4960489 (1990-10-01), Roeska et al.
patent: 5164332 (1992-11-01), Kumar
patent: 5192713 (1993-03-01), Harada
patent: 5202579 (1993-04-01), Fujii et al.
patent: 5216282 (1993-06-01), Cote et al.
patent: 5219639 (1993-06-01), Sugawara et al.

Affiliated with

Also associated with

Rating

Self-aligned via and contact interconnect manufacturing method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Self-aligned via and contact interconnect manufacturing method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self-aligned via and contact interconnect manufacturing method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-628452