Self-aligned trench isolation for memory array using sidewall sp

Details Self-aligned trench isolation for memory array using sidewall sp Self-aligned trench isolation for memory array using sidewall sp

1996-06-24

1997-12-09

Dang, Trung

Fishing, trapping, and vermin destroying

437 52, 437 72, 198DIG50, H01L 2176

Patent

active

056960190

ABSTRACT:
A self-aligned trench isolation technique is provided which produces narrower source and drain regions and isolation structures through the use of sidewall spacers. The process involves forming a multilayer structure over a silicon substrate which includes a conductive material, an insulating material, and a first protective layer. A photoresist masking process is performed on the multilayer structure to define columns of the multilayer structure. A second protective layer is then deposited and etched back to form sidewall spacers adjacent the columns of the multilayer structure. The width of the sidewall spacers is used to define the width of the source and drain regions. Isolation trenches are made using a high selectivity etch which etches through the silicon substrate faster than the protective layers forming the sidewall spacers and covering the columns of the multilayer structure. The isolation trenches are filled with an insulating material, optionally using an etch back step to planarize the insulating layer.

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Aritome, et al., "A 0.67 .mu.m.sup.2 Self-Aligned Shallow Trench Isolation Cell(SA-STI Cell) For 3V-only 256Mbit NAND EEPROMs," IEDM, pp. 61-64, (1994).
Kato, et al., "A 0.4.mu.m.sup.2 Self-Aligned Contactless Memory Cell Technology Suitable for 256-Mbit Flash Memories," IEDM, pp. 921-923, (1994).

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