Self-aligned transistor method

Details Self-aligned transistor method Self-aligned transistor method

1987-03-30

1988-03-01

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 67, 437241, H01L 21265

Patent

active

047286067

ABSTRACT:
A process is described for producing semiconductor devices using a single master mask which determines the lateral dimensions of certain critical device and/or device contact regions in combination with a surrounding isolation wall. Various dielectric layers and isotropic and anisotropic etching steps are utilized in combination with a series of block-out masks to permit etching of a trench in the location of the peripheral isolation wall image in the master mask which is subsequently filled with a dielectric-semiconductor combination. For the case of a vertical bipolar transistor, a base region is implanted using an oversize selector mask. Successive block-out masks are then used to select the particular openings in the master mask which will form the base contact, the emitter and emitter contact and the collector contact. No precision alignments are required between the master mask and the selector or block-out masks. The described method is well suited to the production of transistors, in VLSI applications having minimum lateral dimensions in the micron to submicron range.

REFERENCES:
patent: 4433470 (1984-02-01), Kameyama et al.
patent: 4462846 (1984-07-01), Varshney
patent: 4538343 (1985-09-01), Pollack
patent: 4580330 (1986-04-01), Pollack et al.

Affiliated with

Also associated with

Rating

Self-aligned transistor method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Self-aligned transistor method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self-aligned transistor method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-997680