Self-aligned transistor contact for epitaxial layers

Details Self-aligned transistor contact for epitaxial layers Self-aligned transistor contact for epitaxial layers

1998-10-07

2001-05-29

Loke, Steven (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Bipolar transistor structure

With base region having specified doping concentration...

C257S593000

Reexamination Certificate

active

06239477

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to semiconductor devices and related processing, and more particularly to the formation of self-aligned contact structures for bipolar junction transistors, and the process for making the same.
BACKGROUND OF THE INVENTION
The use of an epitaxial base in a BJT can provide the advantage of increased control over base doping concentrations, which results in narrower bases with reduced transit times and lower peripheral base dopant concentrations for reduced base-emitter capacitances (Cje). These characteristics generally enhance the performance of the resulting device. However, epitaxial bases are difficult to integrate into double polysilicon self-aligned (DPSA) BJT's. If the epitaxial base is deposited prior to the base polysilicon, then the epitaxial base can be damaged or removed by the base polysilicon etch. Alternatively, deposition of the epitaxial base after the emitter region etch requires selective epitaxy processing. Even with selective epitaxy processing, side-wall depositions on the base polysilicon can affect the final emitter region sizing.
One remedy for this issue is to deposit the epitaxial layer and pattern a silicon dioxide (SiO
2
) etch stop prior to the base polysilicon deposition. The emitter opening can then be formed without damaging the underlying epitaxial layer. The structure resulting from this double polysilicon non self-aligned (DPNSA) process is illustrated in FIG.
1
.
In this known structure, the base diffusion (originating from the polysilicon-epitaxy interface) is needed to reduce the higher resistance base epitaxy region in order to achieve a low resistance base layer for desired contact performance. This base diffusion cannot not overlap the emitter diffusion (originating from the emitter polysilicon-base epitaxy interface) without significantly increasing Cje, reducing base-emitter breakdown (BVebo) and negatively impacting reliability. Since the extrinsic base diffusion process is separated from the base contact by the size of the overlap of the etch-stop region over the emitter region, and since this overlap is affected by lithographic sizing variations as well as alignment errors, the drawn overlap must be equal to the total of the widths due to the base diffusion, emitter diffusion, sizing variation, and maximum alignment error. For this reason, the base link-up resistance and the total device area will be larger than achieved in a standard DPSA structure.
A DPNSA BJT is shown in
FIG. 1
, and a dual poly self-aligned (DPSA) BJT is shown in FIG.
2
. In the DPNSA BJT of
FIG. 1
, the distance between the inside edge
20
(outside edge of the emitter window) of the base-emitter spacer
22
to the edge
24
of the isolation structure
26
is designed to include the base link-up diffusion width (or spacer width) “A,” the emitter to etch stop alignment “B,” the pad to field alignment “C,” and the minimum width for extrinsic base diffusion (or extrinsic base junction depth) “D.” Each of these dimensions is approximately 0.1 microns, requiring the edge of the emitter window to be positioned at a minimum of 0.4 microns away from the border
24
of the isolation structure
26
to allow for maximum deviation in processing.
In the DPSA BJT shown in
FIG. 2
, the minimum spacing between the inside edge
28
of the spacer
30
(outside edge of the emitter window) is spaced from the edge
32
of isolation structure
34
by the base link-up diffusion width (spacer width) “A,” the emitter to field alignment “E,” and the minimum width for extrinsic base diffusion (or extrinsic base junction depth) “D.” As each of these dimensions is approximately 0.1 microns, the placement of the edge of the emitter window is designed to allow 0.3 microns variance between its placement and the isolation structure to allow for deviation in the processing.
It is with the foregoing problems in mind that the instant invention was developed.
SUMMARY OF THE INVENTION
The present invention concerns an emitter contact structure for, and associated method for making, a bipolar junction transistor. The emitter contact structure includes a collector region, an intrinsic base region within the collector region, an extrinsic base region within the collector region, a base link-up region within the collector region between the intrinsic base region and the extrinsic base region, a base link diffusion source layer above the base linkup region, a capping layer above the base link diffusion source layer, and a base electrode laterally engaging the extrinsic base region.
In an additional embodiment, the intrinsic, extrinsic and link-up base regions are at a position above the top surface of opposing isolation structures. In a further embodiment, the base electrode is integrally formed with the same layer in which the intrinsic, extrinsic and link-up base regions are formed, and has a laterally disposed, substantially vertically oriented interface with the extrinsic base region.
The inventive method for fabricating the bipolar transistor of the present invention includes the steps of forming opposing isolation structures, and forming a lower collector region positioned between the isolation structures. Then, a silicon layer is integrally deposited over the collector region and the isolation structures to integrally form a polysilicon base electrode over the isolation structures, and an epitaxial silicon region over the lower collector region. The base electrode and the epitaxial silicon have a laterally oriented, substantially vertically disposed junction. The epitaxial silicon region has a bottom layer forming an upper collector, a middle layer forming an intrinsic base region, and an upper layer forming an emitter region. Further, a doped base link diffusion layer is positioned above the base electrode and epitaxial silicon region and the base electrode, and a capping layer is positioned above the base link diffusion source layer. An extrinsic base region is diffused within the epitaxial silicon through the base electrode from the doped base link diffusion source layer, and a base link-up region is formed within the epitaxial silicon region from the base link diffusion source layer to connect the intrinsic base region and the extrinsic base region.
A primary object of the present invention is to provide a bipolar transistor structure that allows a more densely packed design.
Another object of the present invention is to integrally form the base electrode with the region containing the extrinsic, intrinsic, and link-up base regions.
The foregoing and other features, utilities and advantages of the invention will be apparent from the following more particular description of a preferred embodiment of the invention as illustrated in the accompanying drawings.


REFERENCES:
patent: 4851362 (1989-07-01), Suzuki
patent: 5593905 (1997-01-01), Johnson et al.
Article from IEEE Electron Device Letters, vol. 19, No. 5, May 1998, “Effects of Buried Layer Geometry on Characteristics of Double Polysilicon Bipolar Transistors”, pp. 160-162 (Kenneth K.O, Member IEEE and Brad W. Scharf, Member IEEE).

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