Self aligned T-top gate process integration

Details Self aligned T-top gate process integration Self aligned T-top gate process integration

2000-03-06

2002-01-08

Lee, Eddie (Department: 2815)

Semiconductor device manufacturing: process

Forming schottky junction

Compound semiconductor

C438S182000, C438S570000, C438S579000, C438S595000

Reexamination Certificate

active

06337262

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrat circuit devices, and more particularly, to a method for forming a T-Top gate electrode structure.
(2) Description of the Prior Art
Field Effect Devices (FET's) form, in the creation of semiconductor devices, an important class of devices that has, as a consequence, received a considerable amount of attention in its construction and the many refinements that have been applied to this construction. The gate electrode structure forms an essential part of FET devices, this gate electrode is created using repetitive applications of photolithography combined with etch processing steps. This sequence of processing steps is relatively complex and does therefore require close control of tolerances for the proper alignments of the various features that are being created. Incorrect alignment results in increased yield loss and potential problems of device reliability. A method therefore that simplifies this process and that makes the process less dependent on the inherent challenge of using photolithography alignments and the therewith associated steps of plasma etching (a potential source for plasma damage to exposed surfaces) will enhance gate electrode production sequences and improve gate electrode yields, thereby reducing the cost of the device.
The main thrust of the refinements that have been applied to these devices has been provided by the continued decrease in device size, which leads to continued device improvements. In its simplest form, the FET consists of a gate electrode structure, typically formed of polysilicon, that is formed on the surface of a layer of gate oxide that has been deposited on the surface of a semiconductor substrate. Self-aligned with and adjacent to the gate electrode are two regions in the surface of the substrate of opposite conductivity type that are referred to as the source and the drain regions. Points of electrical contact are established to the source and drain regions in addition to the surface region of the gate electrode.
With the continued decrease in device dimensions, it has become increasingly more important to find solutions to problems that are caused by misalignments between the successive mask patterns that are applied to create FET devices. It is for instance of great importance that the source and drain regions are in good alignment with the gate electrode, it is also of great importance that regions to which electrical contacts are to be established are in good alignment in order to assure electrical isolation and the avoidance of electrical shorts between these regions. By using the body of the gate electrode as a mask during ion implantation for the creation of the source and drain regions, good alignment can be obtained for these regions. To separate the source/drain contacts from the contact that is established with the surface of the gate electrode, gate spacers are created on the sidewalls of the gate electrode. To further reduce contact resistance with the points of electrical contact of the gate electrode, these contact regions are salicided. This is accomplished by forming a silicide film of a metal that has a high melting point on these surfaces. A titanium silicide film is mainly used as the high melting point silicide film while cobalt silicide and nickel silicide film have also been investigated. The basic success of forming salicided contact layers can be achieved due to the fact that certain metals, such as titanium or cobalt, react when heated while they are in contact with silicon. This reaction forms conductive silicides over the surface of the silicon while the metal however does not react with silicon oxides. By forming silicon oxide spacers on the sidewalls of the gate electrode, the deposited metal does not interact with the sidewalls of the gate electrode and separate points of electrical contact can be formed for the source/drain regions and the surface of the gate electrode.
For the operation of a FET device, an electrical voltage is applied between the source and the drain regions. Very little current will flow as a result of this electrical voltage because one of the two interfaces (PN junctions) that exist between the underlying silicon substrate and the source/drain regions will always be back biased. The region of the silicon substrate that exists underneath the gate electrode can however be electrically controlled (biased) whereby the minority carriers that are present in this region (the channel region) are increased to a level that is sufficiently high such that this region assumes the same conductivity type as the source/drain regions and, as a consequence, current can flow more freely. Improved FET device performance is achieved by reducing the channel length of the device while simultaneously keeping the resistance between the channel region and the source/drain regions as high as possible. The latter objective is accomplished by the introduction of Lightly Doped Drain (LDD) regions that extend from both sides of the gate electrode with a very light (and not deep) implant into the surface of the substrate.
The formation of an n-type channel MOS device that has salicided source/drain contacts in addition to salicided gate electrode will be detailed in the following section. The process starts with a clean, blank p-type semiconductor surface into which field isolation regions of for instance thick oxide are provided. The field isolation regions bound and define the active regions in the surface of the substrate. Another method of bounding the active areas in the surface of the substrate can establish regions of Shallow Trench Isolation in the surface of the substrate. Next a thin layer of gate oxide is grown over the surface of the substrate by, for instance, using methods of thermal oxidation. A layer of polysilicon is then deposited over the gate oxide layer, this layer of poly is provided with a n-type conductivity and patterned thereby forming the body of the gate electrode. The etch to form the body of the gate electrode removes the layer of poly and the layer of gate oxide in accordance with the pattern of the gate electrode. An n-type ion implant is performed into the surface of the substrate that is self-aligned with the body of the gate electrode, this implant forms the LDD regions of the gate electrode. Gate spacers are next formed in the sidewalls of the body of the gate electrode by a blanket CVD deposition of a layer of silicon oxide over the surface of the gate electrode and its surrounding area. The layer of silicon oxide is anisotropically etched thereby forming the gate spacers. A second (relatively deep and heavily doped) n-type implant is performed into the surface of the substrate, thereby forming the source/drain regions of the gate electrode.
Electrical contacts remain to be established with the source/drain regions and the surface of the gate electrode. A layer of refractory metal is blanket deposited and is subjected to a heat treatment. This heat treatment causes the layer of refractory metal to react with the underlying layer of poly and the underlying surface of the source and drain regions whereby this layer of refractory metal is fully converted to a reacted refractory metal or silicide over these regions. The unreacted refractory metal has not formed silicide and is therefore removed (essentially from the surface of the gate electrode spacers) leaving the silicided metal in place over the surface of the source/drain regions and over the surface of the gate electrode.
The Prior Art gate electrode can then be completed by depositing a layer of dielectric over the surface of the structure, by etching openings through this layer of dielectric whereby these openings align with the source/drain regions and with the top surface of the gate electrode. A layer of metal is then blanket deposited over the surface of the layer of dielectric thereby including the created openings. This latter layer of metal is patterned and etched thereby creating electrical contacts wi

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