Self-aligned super stressed PFET

Details Self-aligned super stressed PFET Self-aligned super stressed PFET

2007-08-21

2010-06-22

Prenty, Mark (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Heterojunction device

Field effect transistor

C257S616000, C257S077000

Reexamination Certificate

active

07741658

ABSTRACT:
The embodiments of the invention comprise a self-aligned super stressed p-type field effect transistor (PFET). More specifically, a field effect transistor comprises a channel region comprising N-doped material and a gate above the channel region. The field effect transistor also includes a source region on a first side of the channel region and a drain region on a second side of the channel region opposite the first side. The source and drain regions each comprise silicon germanium, wherein the silicon germanium has structural indicia of epitaxial growth.

REFERENCES:
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patent: 6844227 (2005-01-01), Kubo et al.
patent: 6927414 (2005-08-01), Ouyang et al.
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patent: 7138292 (2006-11-01), Mirabedini et al.
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patent: 2005/0023520 (2005-02-01), Lee et al.
patent: 2007/0045729 (2007-03-01), Hoentschel et al.

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