Self-aligned stacked CMOS

Details Self-aligned stacked CMOS Self-aligned stacked CMOS

1983-06-17

1985-11-19

James, Andrew J.

357 237, 357 59, 357 71, 357 4, H01L 2702

Patent

active

045545723

ABSTRACT:
A CMOS device configuration in which a complete CMOS inverter is contained in the space normally required for a single NMOS transistor of equivalent geometry. A first polysilicon layer of normal thickness and N+ doping is used for the N channel gate, and a second polysilicon layer is deposited conformally over the oxide which encapsulates the first polysilicon layer. The second polysilicon layer is thin and doped p-type. The second layer is only lightly doped initially, and is then doped more heavily by a low-energy implantation. The portions of the second poly layer which are adjacent to the sidewalls of the gate level in first poly will be shielded from the heavy implantation, and will therefore provide relatively lightly doped p-type channel regions, to form a pair of PMOS polysilicon transistors addressed by the N+ first poly gate electrode. Preferably the channel doping of these polysilicon transistors is at least 10.sup.17. Silicide strapping is optionally used on the remainder of the second poly level to improve its conductivity.

REFERENCES:
patent: 4272880 (1981-06-01), Pashley
patent: 4309224 (1982-01-01), Shibata
patent: 4336550 (1982-06-01), Medwin
patent: 4476475 (1984-10-01), Naem et al.

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