Self-aligned split gate eprom process

Details Self-aligned split gate eprom process Self-aligned split gate eprom process

1986-08-22

1989-01-03

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 44, 437 48, 437 49, 437 52, 437200, 437984, H01L 2710

Patent

active

047957190

ABSTRACT:
A self-aligned split gate single transistor memory cell structure is formed by a process which self aligns the drain region to one edge of a floating gate. The portion of the channel underneath the floating gate is accurately defined by using one edge of the floating gate to align the drain region. The control gate formed over the floating gate controls the portion of the channel region between the floating gate and the source to provide split gate operation. The source region is formed sufficiently far from the floating gate so that the channel length between the source region and the closest edge of the floating gate is controlled by the control gate but does not have to be accurately defined.

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