Self-aligned source/drain MOS process

Details Self-aligned source/drain MOS process Self-aligned source/drain MOS process

1994-07-13

1995-08-08

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437909, 437984, 257336, 257344, H01L 21266, H01L 218234

Patent

active

054398398

ABSTRACT:
A self-aligned contact process for making an MOS device results in an MOS device with a small and repeatable interconnect size, repeatable interconnect resistance, and reduced source/drain junction capacitance.

REFERENCES:
patent: 5328862 (1994-07-01), Goo
patent: 5358879 (1994-10-01), Brady et al.
Hori et al., "A Self-Aligned Pocket Implantation (SPI) Technology for 0.2 micron Dual-Gate CMOS", IEEE Electron Device Letters, vol. 13, No. 4, Apr. 1992, pp. 174-176.
"Simplified Lightly Doped Drain Process", IBM Technical Disclosure Bulletin, vol. 30, No. 12, May 1988, pp. 180-181.

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