Self-aligned single-mask CMOS/BiCMOS twin-well formation with fl

Details Self-aligned single-mask CMOS/BiCMOS twin-well formation with fl Self-aligned single-mask CMOS/BiCMOS twin-well formation with fl

1991-12-30

1993-10-12

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 56, 437 57, 437 89, 257371, H01L 21265

Patent

active

052525015

ABSTRACT:
A single-mask self-aligned process is disclosed for formation of n and p wells for advanced CMOS and BiCMOS technologies. The proposed process forms n-well and p-well regions using a single microlithography masking step along with a selective semiconductor (Si or GeSi) growth SSG process without producing surface topography or degrading device surface planarity. This simple process ensures uniform and repeatable NMOS and PMOS gate patterning due to flat surface topography. The n-to-p well placement and spacing is self-aligned due to the use of a disposable SSG hard mask.

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patent: 4527325 (1985-09-01), Geipel, Jr. et al.
patent: 4558508 (1985-12-01), Kinney et al.
patent: 5132241 (1992-07-01), Su

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