Self-aligned silicon carbide LMOSFET

Details Self-aligned silicon carbide LMOSFET Self-aligned silicon carbide LMOSFET

1999-12-21

2001-11-27

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Specified wide band gap semiconductor material other than...

Diamond or silicon carbide

C257S288000

Reexamination Certificate

active

06323506

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to lateral metal-oxide-semiconductor field effect transistors (LMOSFETs) used in high-power applications such as UHF transmission which are especially suited for silicon carbide (SiC) technology. In particular, the invention relates to a SiC LMOSFET having a self-aligned gate structure and a method of fabricating same.
BACKGROUND OF THE INVENTION
In recent years, the use of silicon lateral double-diffused metal-oxide-semiconductor field effect transistors (Si LDMOSFETs) in high-power and high-frequency applications has increased enormously. This is because Si LDMOSFETs offer simpler gate drive and faster response than bipolar devices.
Si LDMOSFETs are typically fabricated using self-aligned techniques, which minimize gate overlap of the source and drift/drain regions. Minimal overlap is critical for maintaining low gate-to-source and gate-to-drift/drain capacitances, which can adversely affect the high frequency performance of the device. It is also desirable to reduce the overlap to decrease the cell pitch and conserve the silicon area used by the device.
FIG. 1
is a cross-sectional view of a typical Si LDMOSFET
10
fabricated using self-aligned gate techniques. Such techniques involve defining a gate metal
12
(polysilicon) on top of the gate oxide
11
prior to forming the other structures of the device. Once the gate metal
12
has been defined, N+ source and drain regions
13
,
14
, a P base region
15
, and an N− drift region
16
are fabricated by diffusing the N+ source region
13
and the P base region
15
from the source side of the wafer
17
, and diffusing the N− drift region
16
and the N+ drain region
14
from the drain side of the wafer
17
, thus self-aligning the source, base, drain and drift regions
13
,
15
,
14
,
16
with the gate metal
12
. Because the diffusion temperatures used in silicon-based technology are only about 900-1000° C., the gate metal
12
and gate oxide
11
are not adversely affected.
Silicon carbide (SiC) is an attractive semiconductor material for high frequency and high power applications. The properties which make SiC attractive for high power UHF applications are its large critical electric field (10 times that of Si) and its large electron saturation velocity (2 times that of Si). The large critical electric field helps increase the breakdown voltage of the device and the large saturation velocity helps increase the peak current.
Theoretically, it should be possible to achieve power densities which are 20 times higher than that of Si LDMOSFETs with comparable feature sizes in SiC LDMOSFETs. The operating frequency and gain should be similar for both Si and SiC devices with comparable gate lengths. Hence, it would be desirable to fabricate the LDMOSFET
10
shown in
FIG. 1
in SiC instead of Si.
Unfortunately, there are many practical difficulties in achieving the LDMOSFET
10
of
FIG. 1
in SiC. One difficulty is that it is not possible to diffuse the dopants in SiC, thus only high energy ion implantation can be used to fabricate source, base, drift and drain regions. However, implanted dopants in SiC require implantation activation temperatures in excess of 1500° C. Both the gate oxide and gate metal are incapable of withstanding such high temperatures. Consequently, the source, drain, base and drift regions must be activated before fabricating the gate oxide and gate metal. This in turn, undesirably results in a device structure which is no longer self-aligned as the gate metal is fabricated after source and drain fabrication.
Another difficulty in achieving the device structure
10
of
FIG. 1
in SiC concerns the formation of the channel. The channel
19
of the Si LDMOSFET
10
of
FIG. 1
is formed in a diffused P base region
15
. This may not be practical to do in SiC because the inversion layer will be formed in an implanted P base region. Very low inversion layer mobilities (less than 1 cm
2
/Vs) have been achieved in implanted P base regions in SiC. Inversion layer mobilities higher than 100 cm
2
/Vs have only been achieved on epitaxial p-type SiC layers.
FIG. 2
shows a SiC lateral MOSFET (LMOSFET)
20
which attempts to solve the above problems. In this LMOSFET, N+ source, N− drift and N+ drain regions
22
,
24
,
23
are fabricated first in a lightly doped P− epitaxial layer
21
, followed by a gate oxide
25
, and a gate metal
26
. A channel region
27
is defined beneath the gate metal and gate oxide
26
,
25
in the P− epitaxial layer
21
(instead of in a P− base region as in the MOSFET of
10
of FIG.
1
). During fabrication of the gate structure, the gate metal
26
is aligned to the N+ source region
22
and the N− drift region
24
. However, the gate-to-source and gate-to-drift region overlap “x” must be made sufficiently larger than the alignment tolerance. Hence, the overlaps can be anywhere between 0.5 to 2 microns, depending upon the type of alignment tool used.
Although the SiC LMOSFET
20
of
FIG. 2
is operational, it has a number of limitations. In particular, the gate-to-source and gate-to-drift region overlap x of the LMOSFET
20
is much larger than the gate-to-source and gate-to-drift/drain region overlaps in self-aligned Si LDMOSFET structures which typically are about 0.75 times the junction depth and can be made very small.
Further, because the N− drift region
24
is implanted in the P− epitaxial layer
21
, the doping concentration in the drift-region
24
has to be significantly (greater than 5 times) higher than the concentration in the P− epitaxial layer
21
. This puts additional constraints on choice of drift region depth and concentration.
Still further, the SiC LMOSFET of
FIG. 2
suffers from “gate reach-through” as the gate region is formed on top of the lightly doped P− epitaxial layer
21
instead of a highly doped P base region. Moreover, the concentration of N− drift region
24
is higher than the P− epitaxial layer
21
which forces the depletion region to extend farther into the P− epitaxial layer
21
thereby further complicating the problem of gate reach-through.
Additionally, as mentioned earlier, implanted regions in SiC have been shown to have relatively poor mobility in comparison to similarly doped epitaxial layers. Hence, the N− drift region
24
formed in the SiC LMOSFET
20
of
FIG. 2
will undesirably provide higher “on-resistance”.
Therefore, a self-aligned SiC LMOSFET is needed which overcomes the above problems.
SUMMARY OF THE INVENTION
A lateral metal-oxide-semiconductor field effect transistor (LMOSFET) having a self-aligned gate, comprises a first layer of silicon carbide semiconductor material having a p-type conductivity, and a second layer of silicon carbide semiconductor material having an n-type conductivity formed on the first layer. Source and drain regions having n-type conductivities are formed through the second silicon carbide semiconductor layer and can extend partially into the first silicon carbide semiconductor layer. The n-type conductivities of the source and drain regions are greater than the n-type conductivity of the second silicon carbide layer. A trench extends through the second silicon carbide semiconductor layer and partially into the first silicon carbide semiconductor layer so that the source and drain regions are substantially lateral thereto. The trench is coated with a layer of an electrically insulating oxide material and partially filled with a layer of metallic material. The layers of oxide and metallic material form a gate structure. A channel region is defined in the first layer beneath the gate structure, and electrical contacts associated with the source and drain regions, and the gate structure, establish source, drain, and gate electrodes of the LMOSFET.
Another aspect of the invention involves a method for making a LMOSFET with a self-aligned gate. The method comprises providing a wafer including a first layer of silicon carbide semiconducto

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