Self-aligned silicided gate process

Details Self-aligned silicided gate process Self-aligned silicided gate process

1994-05-11

1995-09-05

Quach, T. N.

Fishing, trapping, and vermin destroying

437200, 748DIG15, 748DIG19, H01L 21283, H01L 21336

Patent

active

054478758

ABSTRACT:
A method of forming a self-aligned silicided gate (44) in a semiconductor device (10). A gate electrode having a conductive body (22) and a disposable cap (24) is formed on the surface of the semiconductor body. A sidewall spacer (32) is formed on the sidewall edges of the gate electrode. A surface dielectric (36) is formed over the exposed semiconductor surface adjacent the sidewall spacers (32) and field insulating layer (18). The disposable cap (24) prevents dielectric formation over gate electrode (22). Source/drain junction regions (34) are formed by ion implantation or another suitable doping method in the surface of the semiconductor body adjacent the gate electrode. The disposable cap (24) is then selectively removed and a silicide layer (40) is formed over the gate electrode using a self-aligned silicide react process. An optional additional self-aligned silicide process may be used to form a source/drain junction silicide layer which is thinner than the gate silicide layer (40).

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Wolf, S., Silicon Processing, vol. 2, 1990, Lattice Press, pp. 17-23, 144-151, 380-385.

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