Self-aligned silicide process

Details Self-aligned silicide process Self-aligned silicide process

1993-05-11

1994-06-21

Quach, T. N.

Fishing, trapping, and vermin destroying

437 44, 437190, 437200, 437242, 748DIG19, 748DIG147, H01L 21336, H01L 21283

Patent

active

053228090

ABSTRACT:
A self-aligned silicide process that enables different silicide thicknesses for polysilicon gates and source/drain junction regions. Semiconductor body (10) includes a doped well (14) formed in substrate (12). Field insulating region (18) is located above channel stop region (16) in doped well (14). Implanted within doped well (14) are source/drain junctions (34). Source/drain junctions (34) are shallow heavily doped regions. The surfaces of source/drain junctions (34) are silicided. Silicide gate (44) is separated from the surface of doped well (14) by gate insulator layer (20) and contains a silicide layer (40) and a doped polysilicon layer (22). The thickness of silicide layer (40) is not limited by the thickness of the silicided surfaces of source/drain junctions (34) or the amount of silicon consumed over these junctions. Silicon nitride sidewall spacers (32) separate the sidewall edges of silicide gate (44) and the transistor channel region from the source/drain junction silicide layer 41.

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"Dual Self-Aligned Silicides on FET Gates and Junctions", IBM Tech. Disc. Bull., vol. 31, No. 7, Dec. 1988, p. 154.

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