Self-aligned semiconductor devices

Details Self-aligned semiconductor devices Self-aligned semiconductor devices

1990-09-24

1991-07-02

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 41, 437 40, 437228, 437233, 437584, 357 239, 357 235, 148DIG50, 148DIG141, H01L 2170, H01L 2700

Patent

active

050285556

ABSTRACT:
A novel process is provided for fabricating transistors (14), contacts (46s, 40g, 46d) and interconnections (46c) in a novel self-aligned configuration. The process of the invention permits higher packing densities, and allows feature distances to approach 0.5 .mu.m and lower. In a preferred embodiment, the configuration is also planarized.
A unique combination of masks in conjunction with a multi-layer structure (28) formed on the surface of a semiconductor wafer (16), the multi-layer structure including a buried etch-stop layer therein (28b), defines the source (18), gate (22), and drain (20) elements and their geometry relative to each other and to interconnects. Polysilicon plug (40, 46) contacts through slots in the multi-structure layer permit vertical contact to be made to the various elements. Silicidation (56) of the polysilicon plugs reduces series resistance in the vertical direction and permits strapping of N.sup.+ and P.sup.+ polysilicon plugs.

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patent: 4634496 (1987-01-01), Mase et al.
patent: 4755478 (1988-07-01), Abernathey
patent: 4786609 (1988-11-01), Chen

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