Self-aligned Schottky-barrier clamped planar DMOS transistor...

Details Self-aligned Schottky-barrier clamped planar DMOS transistor... Self-aligned Schottky-barrier clamped planar DMOS transistor...

2007-04-24

2007-04-24

Potter, Roy Karl (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Junction field effect transistor

C257S260000

Reexamination Certificate

active

11014837

ABSTRACT:
The self-aligned Schottky-barrier clamped planar DMOS transistor structure comprises a self-aligned source region being surrounded by a planar gate region. The self-aligned source region comprises a moderately-doped p-base diffusion ring being formed in a lightly-doped N−epitaxial semiconductor layer, a heavily-doped n+source diffusion ring being formed within the moderately-doped p-base diffusion ring, and a Schottky-barrier contact with the moderately-doped p-base diffusion ring acted as a diffusion guard ring being formed in a middle semiconductor surface portion of the self-aligned source region. The planar gate region comprises a patterned heavily-doped polycrystalline-silicon gate layer being silicided with or without metal silicide layers. The self-aligned source region further comprises a lightly-doped p−diffusion region being formed beneath a middle portion of the moderately-doped p-base diffusion ring.

REFERENCES:
patent: 5925910 (1999-07-01), Menegoli

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