Self-aligned row-by-row dynamic VDD SRAM

Details Self-aligned row-by-row dynamic VDD SRAM Self-aligned row-by-row dynamic VDD SRAM

2007-09-04

2007-09-04

Le, Thong Q. (Department: 2827)

Static information storage and retrieval

Powering

C365S230060, C365S154000

Reexamination Certificate

active

11205466

ABSTRACT:
A memory cell array includes a plurality of memory cells arranged in a matrix form. A word line and a power supply line respectively are connected in common to the plurality of memory cells arranged in each row. A power supply line/word line control circuit is connected to each word line and each power supply line. In accessing the plurality of memory cells row by row, the control circuit raises the voltage of the power supply line and, after the voltage of the power supply line reaches the high voltage at all the positions, starts activation of the word line. On the other hand, in turning from the access state to the non-access state, the control circuit deactivates the word line and, after the voltage of the word line changes to the ground voltage at all the positions, changes the voltage of the power supply line to the low voltage.

REFERENCES:
patent: 6301146 (2001-10-01), Ang et al.
patent: 2004/0042326 (2004-03-01), Ashizawa
patent: 2004/0246805 (2004-12-01), Nii
Mai, K.W., et al., “Low-Power SRAM Design Using Half-Swing Pulse-Mode Techniques,”IEEE Journal of Solid-State Circuits 33(11):1659-71, Nov. 1998.

Affiliated with

Also associated with

Rating

Self-aligned row-by-row dynamic VDD SRAM does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Self-aligned row-by-row dynamic VDD SRAM, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self-aligned row-by-row dynamic VDD SRAM will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3730139