Self aligned registration marks for integrated circuit fabricati

Fishing – trapping – and vermin destroying

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

437228, 437200, 437924, H01L 2170

Patent

active

049923943

ABSTRACT:
In order to reduce alignment errors arising in the fabrication of semiconductor integrated circuits using electron beam lithography, enhanced registration marks--(i.e., registration marks that are more easily and accurately detectable by the electron beam)--are formed at the edges of oxide layers, located at the surface of a silicon body, by means of forming metal silicide layers having edges coincident with the edges of the oxide layers. Advantageously, the enhancing of the registgration marks by forming the metal silicide is performed subsequent to any high temperature processing steps, whereby the integrity of the marks is maintained.

REFERENCES:
patent: 4233091 (1980-11-01), Kawabe
IEEE Transactions On Electron Devices, vol. Ed. 28, No. 11, Nov. 1981, "Electron-Beam Lithography for Small MOSFET's", by R. K. Watts et al., pp. 1138-1345.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Self aligned registration marks for integrated circuit fabricati does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Self aligned registration marks for integrated circuit fabricati, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self aligned registration marks for integrated circuit fabricati will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-20434

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.