Self-aligned process for forming dielectrically isolating region

Details Self-aligned process for forming dielectrically isolating region Self-aligned process for forming dielectrically isolating region

1985-09-24

1987-07-14

Ozaki, George T.

Metal working

Method of mechanical manufacture

Assembling or joining

29578, 148187, 148188, 156657, H01L 21385

Patent

active

046793062

ABSTRACT:
A process of fabricating a semiconductor device, wherein a semiconductor substrate of one conductivity type has formed therein layers including a semiconductor layer of the opposite conductivity type, an anti-oxidation mask layer, a doped polysilicon layer, an anti-etch mask layer and a silicon oxide film. Within the substrate are defined isolation areas, from which the silicon oxide film, anti-etch mask layer and doped polysilicon layer are selectively etched away. On the resultant structure is formed an undoped or lightly doped polysilicon layer. Then, the structure is heated to cause atoms of the impurity in the doped polysilicon layer to diffuse into the directly adjacent portions of the undoped or lightly doped polysilicon layer. The undoped or lightly doped polysilicon layer is then etched away over its areas on the silicon oxide film and on the device isolation areas of the substrate. The anti-oxidation mask layer is partially etched away. An exposed portion of the semiconductor layer on the substrate, silicon oxide film, and exposed portions of the undoped or lightly doped polysilicon layer are then etched away. The anti-oxidation mask layer is selectively etched away with the anti-etch mask layer being used as a mask. The residual portions of the anti-oxidation mask layer are then used as a mask to form dielectric regions in the isolation areas of the structure.

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