Self-aligned power field effect transistor in silicon carbide

Details Self-aligned power field effect transistor in silicon carbide Self-aligned power field effect transistor in silicon carbide

1997-06-30

1999-03-02

Trinh, Michael

Semiconductor device manufacturing: process

Having diamond semiconductor component

438268, 438305, 438590, 438931, H01L 2100, H01L 21336

Patent

active

058770410

ABSTRACT:
The present invention is directed to a silicon carbide field effect transistor. The FET is formed on a silicon carbide monocrystalline substrate. An insulative material gate having a pair of spaced apart sidewalls is patterned on the substrate. The insulative material comprises a first insulation material overlayed by an electrically conductive layer. Within the substrate is lightly doped base regions located partially under the sidewalls of the gate and extending into the exposed substrate. Associated with the lightly doped base regions are heavily doped source regions aligned with the exposed substrate. On the underside of the substrate is a drain region to form the FET. Further in accordance with the present invention, a method to fabricate a field effect transistor is disclosed. The transistor is formed in a monocrystalline substrate of silicon carbide. Forming a transistor on the silicon carbide substrate entails depositing a first electrically insulative layer over the substrate. Next, an electrically conductive layer is deposited over the first insulative layer and then a second electrically insulative layer is deposited over the conductive layer. The following step includes partially removing the second insulative layer and exposing a portion of the first conductive layer to obtain two spaced apart regions of the silicon carbide substrate for forming lightly doped base regions. Then the substrate aligned with the exposed portion of the first conductive layer is lightly implanted with a dopant to form lightly doped base regions. Next, a layer of a third insulative material is formed on the sidewalls of the second insulative material. The following step entails removing the exposed conductive layer not aligned with the second insulative material and third insulative material. Thereby, exposing portions of the first insulating layer and defining a second set of spaced regions of the substrate. The second set of spaced regions are then heavily implanted to form heavily doped source regions. The second insulative material and third insulative material are then removed to form a gate.

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patent: 5393999 (1995-02-01), Malhi
patent: 5395780 (1995-03-01), Hwang
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patent: 5597744 (1997-01-01), Kamiyama et al.
patent: 5629531 (1997-05-01), Palmour

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