Self-aligned polysilicon polish

Details Self-aligned polysilicon polish Self-aligned polysilicon polish

2002-05-15

2003-08-26

Ho, Hoai (Department: 2818)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

On insulating substrate or layer

C438S257000, C438S258000, C438S259000, C438S260000, C438S261000, C438S264000, C438S267000, C438S296000, C438S318000

Reexamination Certificate

active

06610577

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor processing, and more particularly to a method for removing polysilicon from isolation regions when forming floating gates in a memory core by polishing the polysilicon such that the remaining polysilicon is self-aligned to trench isolation structures,
BACKGROUND OF THE INVENTION
Flash memory chips are conveniently packaged as “flash cards,” using PC Card, CompactFlash, Smart Media and similar formats. Flash memory has become widely used as film in digital cameras as well as auxiliary storage in a variety of handheld commercial and consumer devices. As illustrated in
FIG. 1
, a conventional flash memory
10
typically includes one or more a high-density core areas
12
and a low density periphery area
14
on a single substrate
16
. The core area includes at least one NxM array of memory transistors for storing data, while the periphery area
16
of the flash memory
10
includes switching logic.
The memory transistors in the core
12
each have a substantially similar stacked gate structure, where the stacked gate structure includes a floating gate comprising a type-1 layer of polysilicon (poly 1) underneath a control gate, which comprises a type-2 layer of polysilicon (poly 2). The layer of poly 2 also forms word lines and select lines in the flash memory array. The transistors in the periphery area
16
have only one gate comprising a layer of poly 2. Thus, these transistors are referred to as poly 2 transistors.
The major processing steps for fabricating a flash memory array begin by patterning a nitride mask to define alternating columns of active device regions and isolations regions on a substrate. For sub-micron devices, shallow trench isolation is used to form shallow trenches in the substrate in between the active regions to create isolation regions in both the periphery and core areas
12
. After the shallow trenches are formed, a layer of liner oxide is grown in the trenches, followed by a deposition of an isolation dielectric, such as oxide to fill the trenches. After the trench oxide is deposited, the trench oxide is polished back using a chemical mechanical polish (CMP) so that the oxide remains only in the trenches, its top surface slightly recessed with the previously etched nitride mask. After the trench oxide is polished, the nitride mask is stripped, and a layer of polysilicon is deposited in both the core
12
and periphery
14
. In the memory core
12
, floating gates will be patterned and etched in the conventional processing approach with some positional variability due to lithographic positional overlay error. Eventually, the polysilicon in the periphery
14
will be removed, followed by the deposition of poly 2 to form both the stacked gate structures in the core
12
, and the poly 2 transistors in the periphery
14
.
FIG. 2
is a perspective view (not to scale and not including core gate dielectrics or interpoly layer dielectrics) of a portion of the memory array in the core region
12
at a stage in fabrication prior to poly 2 deposition. In order to form the floating gates, the layer of the polysilicon
18
must be etched away from the trench isolation regions
20
, leaving the polysilicon
18
only in the active regions, as shown.
Previous techniques for etching the polysilicon
18
include depositing a layer photoresist over the layer of polysilicon
18
, and patterning the photoresist using lithographic techniques to form a mask. Using the mask, the polysilicon
18
is etched to form parallel lines of polysilicon
18
that will be used to form floating gates. Thereafter, the photoresist mask is removed.
Although this technique is effective for etching the polysilicon
18
, the mask and etch technique inherently results in alignment errors due to lithographic limitations. Therefore, when the design rules for tolerances are specified, transistor spacing on the substrate must be sacrificed to ensure that the columns of polysilicon
18
overlap the isolation regions. Otherwise, if a mask alignment error were to occur, too much of the polysilicon
18
may be etched away from the isolation regions
20
, leaving portions of the substrate
16
exposed, which results in faulty semiconductor devices.
An improved mask and etch technique has recently been developed for patterning materials during semiconductor fabrication that is capable of surpassing lithographic limitations in which a hard mask is substituted for the photoresist mask. Although the hard mask approach allows the spaces between the polysilicon
18
to be closer together, the hard mask approach is complex and adds to the number of processing steps.
Accordingly, what is needed is an improved method for removing the polysilicon from the isolation regions without the complexities of a hard mask. The present invention addresses such a need.
SUMMARY OF THE INVENTION
The present invention provides a method for removing polysilicon from isolation regions on a substrate during semiconductor fabrication. The method includes depositing a layer of polysilicon over the substrate, and depositing at least one dielectric layer over the polysilicon. The method further includes removing the dielectric from the memory core and polishing the polysilicon from memory core isolation regions between memory cells, while the dielectric layers act as a polishing stop in periphery areas. This results in regions of floating gate polisilicon that are self-aligned to the trench isolation regions.
According to the method disclosed herein, by depositing dielectric layers over the polysilicon, lines of polysilicon that are self-aligned to trench isolation structures are provided in the memory core, while non-uniform polysilicon polish in the periphery is prevented. Defining self-aligned polysilicon floating gate structures increases memory core transistor density, and improves polysilicon capacitive coupling uniformity to the substrate, valuable in programming and erasing the cells in circuit operation.


REFERENCES:
patent: 6013551 (2000-01-01), Chen et al.

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