Patent
1990-09-27
1992-01-14
Larkins, William D.
357 239, 357 59, 357 67, 357 71, H01L 23522, H01L 27105
Patent
active
050815164
ABSTRACT:
A novel process is provided for fabricating contacts (46s, 40g, 46d) in a novel, completely self-aligned, planarized configuration for transistors (14), with self-aligned interconnections (46c). The process of the invention permits high packing densities, and allows feature distances to approach 0.5 .mu.m and lower. A unique combination of masks in conjunction with a multi-layer structure (28) formed on the surface of a semiconductor wafer (16), the multi-layer structure including a buried etch-stop layer therein (28b), defines the source (18), gate (22), and drain (20) elements and their geometry relative to each other and to interconnects. Polysilicon plug (40, 46) contacts through slots in the multi-structure layer permit vertical contact to be made to the various elements. Silicidation (56) of the polysilicon plugs reduces series resistance in the vertical direction and permits strapping of N.sup.+ and P.sup.+ polysilicon plugs.
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patent: 4729006 (1988-03-01), Dally et al.
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Advanced Micro Devices , Inc.
Larkins William D.
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