Self-aligned planar monolithic integrated circuit vertical trans

Details Self-aligned planar monolithic integrated circuit vertical trans Self-aligned planar monolithic integrated circuit vertical trans

1991-06-18

1992-07-07

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 28, 437 55, 437162, 437909, 148DIG10, H01L 21265

Patent

active

051282720

ABSTRACT:
A process for creating self-aligned vertically arrayed planar transistors. The preferred embodiment relates to the simultaneous fabrication of both NPN and PNP planar vertically arrayed transistors in a conventional monolithic, epitaxial, PN junction isolated, integrated circuit. A field oxide is employed to surface isolate the devices and assist in the self-alignment improvement.

REFERENCES:
patent: 4110126 (1978-08-01), Bergeron et al.
patent: 4375999 (1983-03-01), Nawata et al.
patent: 4910160 (1990-03-01), Jennings et al.
patent: 4933295 (1990-06-01), Feist
patent: 4940671 (1990-07-01), Small et al.
patent: 5013672 (1991-05-01), Zambrano

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